Abstract: A system and method are provided for performing transmission control protocol segmentation on a server on a chip using coprocessors on the server chip. A system processor manages the TCP/IP stack and prepares a large (64 KB) single chunk of data to be sent out via a network interface on the server on a chip. The system software processes this and calls the interface device driver to send the packet out. The device driver, instead of sending the packet out directly on the interface, calls a coprocessor interface and delivers some metadata about the chunk of data to the interface. The coprocessor segments the chunk of data into a maximum transmission unit size associated with the network interface and increments a sequential number field in the header information of each packet before sending the segments to the network interface.

Abstract: Various embodiments provide for a system on a chip or a server on a chip that performs flow pinning, where packets or streams of packets are enqueued to specific queues, wherein each queue is associated with a respective core in a multiprocessor/multi-core system or server on a chip. With each stream of packets, or flow, assigned to a particular processor, the server on a chip can process and intake packets from multiple queues from multiple streams from the same single Ethernet interface in parallel. Each of the queues can issue interrupts to their assigned processors, allowing each of the processors to receive packets from their respective queues at the same time. Packet processing speed is therefore increased by receiving and processing packets in parallel for different streams.

Abstract: Various aspects of the present disclosure provide for a system that is able to boot from a variety of media that can be connected to the system, including SPI NOR and SPI NAND memory, universal serial bus (“USB”) devices, and devices attached via PCIe and Ethernet interfaces. When the system is powered on, the system processor is held in a reset mode, while a microcontroller in the system identifies an external device to be booted, and then copies a portion of boot code from the external device to an on-chip memory. The microcontroller can then direct the reset vector to the boot code in the on-chip memory and brings the system processor out of reset. The system processor can execute the boot code in-place on the on-chip memory, which initiates the system memory and the second stage boot loader.

Abstract: Various aspects provide large receive offload (LRO) functionality for a system on chip (SoC). A classifier engine is configured to classify one or more network packets received from a data stream as one or more network segments. A first memory is configured to store one or more packet headers associated with the one or more network segments. At least one processor is configured to receive the one or more packet headers and generate a single packet header for the one or more network segments in response to a determination that a gather buffer that stores packet data for the one or more network segments has reached a predetermined size.

Abstract: Various embodiments provide for a system on a chip or a server on a chip that performs flow pinning, where packets or streams of packets are enqueued to specific queues, wherein each queue is associated with a respective core in a multiprocessor/multi-core system or server on a chip. With each stream of packets, or flow, assigned to a particular processor, the server on a chip can process and intake packets from multiple queues from multiple streams from the same single Ethernet interface in parallel. Each of the queues can issue interrupts to their assigned processors, allowing each of the processors to receive packets from their respective queues at the same time. Packet processing speed is therefore increased by receiving and processing packets in parallel for different streams.

Abstract: A system and method are provided for performing transmission control protocol segmentation on a server on a chip using coprocessors on the server chip. A system processor manages the TCP/IP stack and prepares a large (64 KB) single chunk of data to be sent out via a network interface on the server on a chip. The system software processes this and calls the interface device driver to send the packet out. The device driver, instead of sending the packet out directly on the interface, calls a coprocessor interface and delivers some metadata about the chunk of data to the interface. The coprocessor segments the chunk of data into a maximum transmission unit size associated with the network interface and increments a sequential number field in the header information of each packet before sending the segments to the network interface.

Abstract: A hardware-based method is provided for allocating shared resources in a system-on-chip (SoC). The SoC includes a plurality of processors and at least one shared resource, such as an input/output (IO) port or a memory. A queue manager (QM) includes a plurality of input first-in first-out memories (FIFOs) and a plurality of output FIFOs. A first application writes a first request to access the shared resource. A first application programming interface (API) loads the first request at a write pointer of a first input FIFO associated with the first processor. A resource allocator reads the first request from a read pointer of the first input FIFO, generates a first reply, and loads the first reply at a write pointer of a first output FIFO associated with the first processor. The first API supplies the first reply, from a read pointer of the first output FIFO, to the first application.

Abstract: Various aspects provide large receive offload (LRO) functionality for a system on chip (SoC). A classifier engine is configured to classify one or more network packets received from a data stream as one or more network segments. A first memory is configured to store one or more packet headers associated with the one or more network segments. At least one processor is configured to receive the one or more packet headers and generate a single packet header for the one or more network segments in response to a determination that a gather buffer that stores packet data for the one or more network segments has reached a predetermined size.

Abstract: Various aspects of the present disclosure provide for a system that is able to boot from a variety of media that can be connected to the system, including SPI NOR and SPI NAND memory, universal serial bus (“USB”) devices, and devices attached via PCIe and Ethernet interfaces. When the system is powered on, the system processor is held in a reset mode, while a microcontroller in the system identifies an external device to be booted, and then copies a portion of boot code from the external device to an on-chip memory. The microcontroller can then direct the reset vector to the boot code in the on-chip memory and brings the system processor out of reset. The system processor can execute the boot code in-place on the on-chip memory, which initiates the system memory and the second stage boot loader.