Abstract: A high performance microprocessor bus protocol for improving system throughput. The bus protocol enables overlapping read burst and write burst bus transactions to a cache, and interleaved bus transactions during external fetch cycles for missed cache lines. The bus protocol is implemented in a system comprising a CPU, and a secondary cache. The secondary cache comprises an SRAM array cache, and a cache controller. The CPU contains an instruction pipeline and a primary cache system.

Abstract: A dynamic random access memory (DRAM) single in-line memory module (SIMM) having optimized physical dimensions achieves high speed and high storage capacity. The DRAM SIMM has a printed circuit board with a multi-contact connector, a plurality of DRAM sets, each set having a plurality of DRAM chips mounted on the printed circuit board, and a plurality of buffers which are also mounted on the printed circuit board. The number of buffers is equal to the number of DRAM sets. Various standard DRAM chips can be used on the SIMM to achieve different performance and storage capacity, while maintaining plug compatibility of the multi-contact connector with a memory board. The buffers buffer the control and address signals for the DRAM chips, which is necessary to keep control and address signal integrity due to the number of DRAMS. The buffers permit each DRAM to receive the necessary control and address signals in a more synchronized fashion, so that relative delays are well controlled.