Patents by Inventor Kumara Tharmalingam
Kumara Tharmalingam has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10650071Abstract: A digital content acceleration system comprising: a keyed database for storing keyed data; a data retrieval engine that retrieves, in response to receiving an item of keyed data, one of i) search data indicative of a search history associated with the item of keyed data, ii) web history data indicative of one or more web pages accessed by a terminal device associated with the item of keyed data, or iii) both i) and ii); a parsing engine that extracts one or more attributes from the search data and the web history data; a terminal device network access engine that generates, based on the one or more attributes, a probability distribution for geographic locations; a content selection engine that retrieves, from a digital content provider, digital content associated with a particular geographic location of the geographic locations; and a digital content assembler engine that pre-assembles the digital content.Type: GrantFiled: December 14, 2016Date of Patent: May 12, 2020Assignee: Google LLCInventors: Amogh S. Asgekar, Piyush Prahladka, Kumara Tharmalingam
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Publication number: 20180150565Abstract: A digital content acceleration system comprising: a keyed database for storing keyed data; a data retrieval engine that retrieves, in response to receiving an item of keyed data, one of i) search data indicative of a search history associated with the item of keyed data, ii) web history data indicative of one or more web pages accessed by a terminal device associated with the item of keyed data, or iii) both i) and ii); a parsing engine that extracts one or more attributes from the search data and the web history data; a terminal device network access engine that generates, based on the one or more attributes, a probability distribution for geographic locations; a content selection engine that retrieves, from a digital content provider, digital content associated with a particular geographic location of the geographic locations; and a digital content assembler engine that pre-assembles the digital content.Type: ApplicationFiled: December 14, 2016Publication date: May 31, 2018Inventors: Amogh S. Asgekar, Piyush Prahladka, Kumara Tharmalingam
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Patent number: 9559881Abstract: A transceiver system with reduced latency uncertainty is described. In one implementation, the transceiver system has a word aligner latency uncertainty of zero. In another implementation, the transceiver system has a receiver-to-transmitter transfer latency uncertainty of zero. In yet another implementation, the transceiver system has a word aligner latency uncertainty of zero and a receiver-to-transmitter transfer latency uncertainty of zero. In one specific implementation, the receiver-to-transmitter transfer latency uncertainty is eliminated by using the transmitter parallel clock as a feedback signal in the transmitter phase locked loop (PLL). In one implementation, this is achieved by optionally making the transmitter divider, which generates the transmitter parallel clock, part of the feedback path of the transmitter PLL.Type: GrantFiled: September 15, 2008Date of Patent: January 31, 2017Assignee: Altera CorporationInventors: Neville Carvalho, Allan Thomas Davidson, Andy Turudic, Bruce B. Pedersen, David W. Mendel, Kalyan Kankipati, Michael Menghui Zheng, Sergey Shumarayev, Seungmyon Park, Tim Tri Hoang, Kumara Tharmalingam
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Patent number: 9395953Abstract: A plurality of specialized processing blocks in a programmable logic device, including multipliers and circuitry for adding results of those multipliers, can be configured as a larger multiplier by adding to the specialized processing blocks selectable circuitry for shifting multiplier results before adding. In one embodiment, this allows all but the final addition to take place in specialized processing blocks, with the final addition occurring in programmable logic. In another embodiment, additional compression and adding circuitry allows even the final addition to occur in the specialized processing blocks.Type: GrantFiled: June 10, 2014Date of Patent: July 19, 2016Assignee: ALTERA CORPORATIONInventors: Martin Langhammer, Kumara Tharmalingam
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Patent number: 9170775Abstract: A multiplier-accumulator (MAC) block can be programmed to operate in one or more modes. When the MAC block implements at least one multiply-and-accumulate operation, the accumulator value can be zeroed without introducing clock latency or initialized in one clock cycle. To zero the accumulator value, the most significant bits (MSBs) of data representing zero can be input to the MAC block and sent directly to the add-subtract-accumulate unit. Alternatively, dedicated configuration bits can be set to clear the contents of a pipeline register for input to the add-subtract-accumulate unit.Type: GrantFiled: January 7, 2010Date of Patent: October 27, 2015Assignee: Altera CorporationInventors: Leon Zheng, Martin Langhammer, Nitin Prasad, Greg Starr, Chiao Kai Hwang, Kumara Tharmalingam
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Patent number: 9063870Abstract: A plurality of specialized processing blocks in a programmable logic device, including multipliers and circuitry for adding results of those multipliers, can be configured as a larger multiplier by adding to the specialized processing blocks selectable circuitry for shifting multiplier results before adding. In one embodiment, this allows all but the final addition to take place in specialized processing blocks, with the final addition occurring in programmable logic. In another embodiment, additional compression and adding circuitry allows even the final addition to occur in the specialized processing blocks. Circuitry that controls when an input is signed or unsigned facilitates complex arithmetic.Type: GrantFiled: January 17, 2013Date of Patent: June 23, 2015Assignee: Altera CorporationInventors: Martin Langhammer, Kumara Tharmalingam
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Publication number: 20140289293Abstract: A plurality of specialized processing blocks in a programmable logic device, including multipliers and circuitry for adding results of those multipliers, can be configured as a larger multiplier by adding to the specialized processing blocks selectable circuitry for shifting multiplier results before adding. In one embodiment, this allows all but the final addition to take place in specialized processing blocks, with the final addition occurring in programmable logic. In another embodiment, additional compression and adding circuitry allows even the final addition to occur in the specialized processing blocks.Type: ApplicationFiled: June 10, 2014Publication date: September 25, 2014Inventors: Martin Langhammer, Kumara Tharmalingam
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Patent number: 8788562Abstract: A plurality of specialized processing blocks in a programmable logic device, including multipliers and circuitry for adding results of those multipliers, can be configured as a larger multiplier by adding to the specialized processing blocks selectable circuitry for shifting multiplier results before adding. In one embodiment, this allows all but the final addition to take place in specialized processing blocks, with the final addition occurring in programmable logic. In another embodiment, additional compression and adding circuitry allows even the final addition to occur in the specialized processing blocks.Type: GrantFiled: March 8, 2011Date of Patent: July 22, 2014Assignee: Altera CorporationInventors: Martin Langhammer, Kumara Tharmalingam
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Patent number: 8612795Abstract: One embodiment relates to a clocking network interconnecting an array of transceivers. The clocking network includes first and second series of multiplexers, each multiplexer in the first and second series being adjacent to a transceiver. The first series of multiplexers selectively transmits clock signals in a first direction of the array, and the second series of multiplexers selectively transmits clock signals in a second direction of the array. Another embodiment relates to an integrated circuit with a programmable interface. The integrated circuit includes an array of physical media attachment circuits, phase-locked loop circuits, and a clock distribution network. The clock distribution network is arranged to be programmed into multiple segments. Each segment distributes a clock signal to a bounded range of the physical media attachment circuits in the array. Another embodiment relates to a method of distributing clock signals in an integrated circuit. Other embodiments and features are also disclosed.Type: GrantFiled: July 30, 2010Date of Patent: December 17, 2013Assignee: Altera CorporationInventors: Weiqi Ding, Kumara Tharmalingam
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Patent number: 8386553Abstract: A plurality of specialized processing blocks in a programmable logic device, including multipliers and circuitry for adding results of those multipliers, can be configured as a larger multiplier by adding to the specialized processing blocks selectable circuitry for shifting multiplier results before adding. In one embodiment, this allows all but the final addition to take place in specialized processing blocks, with the final addition occurring in programmable logic. In another embodiment, additional compression and adding circuitry allows even the final addition to occur in the specialized processing blocks. Circuitry that controls when an input is signed or unsigned facilitates complex arithmetic.Type: GrantFiled: March 6, 2007Date of Patent: February 26, 2013Assignee: Altera CorporationInventors: Martin Langhammer, Kumara Tharmalingam
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Patent number: 8228102Abstract: One embodiment relates to an integrated circuit including a first strip of phase-locked loop (PLL) circuits on a first side of the integrated circuit, and a second strip of PLL circuits on a second side of the integrated circuit which is opposite from the first side. The PLL circuits in the first and second strips may be configured by programming the integrated circuit. Another embodiment relates to an integrated circuit including a plurality of phase-locked loop (PLL) circuits and a plurality of physical media attachment (PMA) triplet modules adjacent to the plurality of PLL circuits. Each PMA triplet module includes first, second and third channels. The first and third channels are arranged for use as receiving channels, and the second channel is arranged to be configurable as either a receiving channel or a clock multiplication unit. Other embodiments and features are also disclosed.Type: GrantFiled: March 3, 2010Date of Patent: July 24, 2012Assignee: Altera CorporationInventors: Tien Duc Pham, Sergey Shumarayev, Richard G. Cliff, Tim Tri Hoang, Weiqi Ding, Sriram Narayan, Thungoc M. Tran, Kumara Tharmalingam
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Patent number: 8171443Abstract: Computer-aided-design tools are provided that support real-time phase-locked loop reconfiguration with a single design compilation. Each design compilation may involve operations such as logic synthesis and place and route operations. A circuit designer who is designing an integrated circuit may supply circuit design data. The circuit design data may include design data for multiple configurations of a phase-locked loop. By using a phase-locked loop scan chain initialization file generator engine located in a CAD tool design input wizard, the computer-aided-design tools may produce multiple phase-locked loop initialization files without performing a design compilation. The CAD tools may process one or more initialization files and the circuit design data to produce output data. The output data may include configuration data to implement the circuit design.Type: GrantFiled: May 18, 2011Date of Patent: May 1, 2012Assignee: Altera CorporationInventors: Ian Eu Meng Chan, Kumara Tharmalingam
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Patent number: 8001537Abstract: During compilation of a user logic design in a first type of programmable logic device (e.g., an FPGA), a log is kept of at least certain steps where choices are made. When that logic design is migrated to another type of programmable logic device (e.g., a mask-programmable logic device) the logged steps are taken into account to make sure that the same choices are made, so that the target device is functionally equivalent to the original device.Type: GrantFiled: December 5, 2005Date of Patent: August 16, 2011Assignee: Altera CorporationInventors: Mihail Iotov, David Neto, Pouyan Djahani, David Karchmer, Kumara Tharmalingam
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Publication number: 20110161389Abstract: A plurality of specialized processing blocks in a programmable logic device, including multipliers and circuitry for adding results of those multipliers, can be configured as a larger multiplier by adding to the specialized processing blocks selectable circuitry for shifting multiplier results before adding. In one embodiment, this allows all but the final addition to take place in specialized processing blocks, with the final addition occurring in programmable logic. In another embodiment, additional compression and adding circuitry allows even the final addition to occur in the specialized processing blocks.Type: ApplicationFiled: March 8, 2011Publication date: June 30, 2011Applicant: ALTERA CORPORATIONInventors: Martin Langhammer, Kumara Tharmalingam
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Patent number: 7949980Abstract: Computer-aided-design tools are provided that support real-time phase-locked loop reconfiguration with a single design compilation. Each design compilation may involve operations such as logic synthesis and place and route operations. A circuit designer who is designing an integrated circuit may supply circuit design data. The circuit design data may include design data for multiple configurations of a phase-locked loop. By using a phase-locked loop scan chain initialization file generator engine located in a CAD tool design input wizard, the computer-aided-design tools may produce multiple phase-locked loop initialization files without performing a design compilation. The CAD tools may process one or more initialization files and the circuit design data to produce output data. The output data may include configuration data to implement the circuit design.Type: GrantFiled: July 31, 2008Date of Patent: May 24, 2011Assignee: Altera CorporationInventors: Ian Eu Meng Chan, Kumara Tharmalingam
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Patent number: 7930336Abstract: A plurality of specialized processing blocks in a programmable logic device, including multipliers and circuitry for adding results of those multipliers, can be configured as a larger multiplier by adding to the specialized processing blocks selectable circuitry for shifting multiplier results before adding. In one embodiment, this allows all but the final addition to take place in specialized processing blocks, with the final addition occurring in programmable logic. In another embodiment, additional compression and adding circuitry allows even the final addition to occur in the specialized processing blocks.Type: GrantFiled: December 5, 2006Date of Patent: April 19, 2011Assignee: Altera CorporationInventors: Martin Langhammer, Kumara Tharmalingam
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Publication number: 20100169404Abstract: A multiplier-accumulator (MAC) block can be programmed to operate in one or more modes. When the MAC block implements at least one multiply-and-accumulate operation, the accumulator value can be zeroed without introducing clock latency or initialized in one clock cycle. To zero the accumulator value, the most significant bits (MSBs) of data representing zero can be input to the MAC block and sent directly to the add-subtract-accumulate unit. Alternatively, dedicated configuration bits can be set to clear the contents of a pipeline register for input to the add-subtract-accumulate unit.Type: ApplicationFiled: January 7, 2010Publication date: July 1, 2010Inventors: Leon Zheng, Martin Langhammer, Nitin Prasad, Greg Starr, Chiao Kai Hwang, Kumara Tharmalingam
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Patent number: 7660841Abstract: A multiplier-accumulator (MAC) block can be programmed to operate in one or more modes. When the MAC block implements at least one multiply-and-accumulate operation, the accumulator value can be zeroed without introducing clock latency or initialized in one clock cycle. To zero the accumulator value, the most significant bits (MSBs) of data representing zero can be input to the MAC block and sent directly to the add-subtract-accumulate unit. Alternatively, dedicated configuration bits can be set to clear the contents of a pipeline register for input to the add-subtract-accumulate unit.Type: GrantFiled: February 20, 2004Date of Patent: February 9, 2010Assignee: Altera CorporationInventors: Leon Zheng, Martin Langhammer, Nitin Prasad, Greg Starr, Chiao Kai Hwang, Kumara Tharmalingam
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Publication number: 20090161738Abstract: A transceiver system with reduced latency uncertainty is described. In one implementation, the transceiver system has a word aligner latency uncertainty of zero. In another implementation, the transceiver system has a receiver-to-transmitter transfer latency uncertainty of zero. In yet another implementation, the transceiver system has a word aligner latency uncertainty of zero and a receiver-to-transmitter transfer latency uncertainty of zero. In one specific implementation, the receiver-to-transmitter transfer latency uncertainty is eliminated by using the transmitter parallel clock as a feedback signal in the transmitter phase locked loop (PLL). In one implementation, this is achieved by optionally making the transmitter divider, which generates the transmitter parallel clock, part of the feedback path of the transmitter PLL.Type: ApplicationFiled: September 15, 2008Publication date: June 25, 2009Applicant: Altera CorporationInventors: Neville Carvalho, Allan Thomas Davidson, Andy Turudic, Bruce B. Pedersen, David W. Mendel, Kalyan Kankipati, Michael Menghui Zheng, Sergey Shumarayev, Seungmyon Park, Tim Tri Hoang, Kumara Tharmalingam
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Patent number: 7545196Abstract: Clocks are distributed efficiently to regions of a specialized processing block in a PLD. Multiple clocks are selected from a larger universe of clocks and distributed to the specialized processing block, but the choices of clocks at the individual functional regions, or stages of functional regions, are less than fully flexible. In some cases, an entire region may use one clock. In another case, portions of a stage within a region that previously had been able to select individual clocks must use one clock for the entire stage. In another case, only a subset of the selected clocks is available for a particular region, but that subset is flexibly distributable within the region. In another case, a clock may be selectable for each stage of each functional region directly from the larger universe of available clocks, avoiding the need for circuitry to select the multiple clocks from the larger universe.Type: GrantFiled: October 17, 2006Date of Patent: June 9, 2009Assignee: Altera CorporationInventors: Michael D. Hutton, Kumara Tharmalingam, Yi-Wen Lin, David Neto