Abstract: A high side current sensing amplifier architecture is simplified and improved over prior art current sensing amplifier circuits by using chopping only, without requiring auto-zeroing, and by using a simpler (and faster) switched capacitor filter instead of an auto-zeroing integrator filter. Also, VIP (positive DC sense node) is merged with the VDDHV (power supply) node, such that the integrated circuit package requires only a single node (package pin) to accommodate both the VIP and VDDHV connections for the current sensing amplifier circuit, resulting in being able to use a smaller integrated circuit package. A small resistor is coupled between VIP and VDDHV to reduce the offset considerably. A low latency time high voltage level shifter is provided which is essential for precise chopping operation.

Abstract: An amplifier includes a differential positive input, a differential negative input, and a transistor. The transistor is communicatively coupled to the differential positive input and differential negative input at a source of the transistor. The transistor is configured to track input common mode of the differential positive input and differential negative input.

Abstract: An amplifier includes a differential positive input, a differential negative input, and a transistor. The transistor is communicatively coupled to the differential positive input and differential negative input at a source of the transistor. The transistor is configured to track input common mode of the differential positive input and differential negative input.

Abstract: A high side current sensing amplifier architecture is simplified and improved over prior art current sensing amplifier circuits by using chopping only, without requiring auto-zeroing, and by using a simpler (and faster) switched capacitor filter instead of an auto-zeroing integrator filter. Also, VIP (positive DC sense node) is merged with the VDDHV (power supply) node, such that the integrated circuit package requires only a single node (package pin) to accommodate both the VIP and VDDHV connections for the current sensing amplifier circuit, resulting in being able to use a smaller integrated circuit package. A small resistor is coupled between VIP and VDDHV to reduce the offset considerably. A low latency time high voltage level shifter is provided which is essential for precise chopping operation.

Abstract: An integrated temperature sensor device has a temperature sensor configured to provide an analog signal corresponding to an ambient temperature, an analog-to-digital converter receiving the analog signal and a programmable digital filter coupled to the analog-to-digital converter.

Abstract: An integrated temperature sensor device has a temperature sensor configured to provide an analog signal corresponding to an ambient temperature, an analog-to-digital converter receiving the analog signal and a programmable digital filter coupled to the analog-to-digital converter.

Abstract: Calibration of gain and/or offset of an instrumentation amplifier (INA) is accomplished by coupling an appropriate number of current sources, and/or current sinks, respectively, to first and/or second transconductance stage(s) of the INA. Gain and/or offset calibration of the INA may occur when requested by a user and/or the occurrence of an event(s). A voltage reference may be used in combination with a successive approximation register analog-to-digital converter in determining which ones of the current sources and sinks are coupled to the first and/or second transconductance stage(s) of the INA for gain and/or offset calibration thereof. After the gain and/or offset calibration of the INA is completed, the selection of the constant current sources and sinks used therefore may be stored in volatile or nonvolatile memory. Parity checking of the memory may be incorporated and if a parity error is detected, an auto-calibration of the INA may be initiated.

Abstract: Calibration of gain and/or offset of an instrumentation amplifier (INA) is accomplished by coupling an appropriate number of current sources, and/or current sinks, respectively, to first and/or second transconductance stage(s) of the INA. Gain and/or offset calibration of the INA may occur when requested by a user and/or the occurrence of an event(s). A voltage reference may be used in combination with a successive approximation register analog-to-digital converter in determining which ones of the current sources and sinks are coupled to the first and/or second transconductance stage(s) of the INA for gain and/or offset calibration thereof. After the gain and/or offset calibration of the INA is completed, the selection of the constant current sources and sinks used therefore may be stored in volatile or nonvolatile memory. Parity checking of the memory may be incorporated and if a parity error is detected, an auto-calibration of the INA may be initiated.

Abstract: Auto-calibration of the analog circuits occurs when requested by a user and/or the occurrence of an event(s). The user may invoke an auto-calibration on demand through an auto-calibration (ACAL) input to the mixed-signal integrated circuit. An external voltage calibration (VCAL) input may be used for auto-calibration of the mixed-signal integrated circuit to a user-supplied common-mode voltage reference. Auto-calibration of the mixed-signal integrated circuit may also be initiated upon the occurrence of any one or more of the following events: 1) detection of auto-calibration data corruption, e.g., parity checking of auto-calibration data values digitally stored in the mixed-signal integrated circuit; 2) an internal timer that causes a calibration request after a programmable timeout period, 3) change in the internal integrated circuit die temperature as determined by a temperature sensor, and 4) a change in the power supply and/or internal supply voltage(s).

Abstract: Two nulling amplifiers are used with an auto-zeroed differential amplifier. While one nulling amplifier is compensating the main amplifier, the other nulling amplifier is being zeroed for both differential mode (DM) and common mode (CM) offsets. By using two nulling amplifiers, one always connected to the main amplifier, a relatively constant open-loop gain is maintained for the main amplifier. A further improvement is make-before-break timing overlap of the switch operations between the two nulling amplifiers and the main amplifier. This ensures that the main amplifier is continuously driven by one or both null amplifiers, thereby maintaining a low impedance at the main amplifier auxiliary port. Both DM and CM offset sampling and precharging of each of the two nulling amplifiers is performed so as to substantially reduce switching glitches in the output of the main amplifier.

Abstract: Two nulling amplifiers are used with an auto-zeroed differential amplifier. While one nulling amplifier is compensating the main amplifier, the other nulling amplifier is being zeroed for both differential mode (DM) and common mode (CM) offsets. By using two nulling amplifiers, one always connected to the main amplifier, a relatively constant open-loop gain is maintained for the main amplifier. A further improvement is make-before-break timing overlap of the switch operations between the two nulling amplifiers and the main amplifier. This ensures that the main amplifier is continuously driven by one or both null amplifiers, thereby maintaining a low impedance at the main amplifier auxiliary port. Both DM and CM offset sampling and precharging of each of the two nulling amplifiers is performed so as to substantially reduce switching glitches in the output of the main amplifier.

Abstract: An amplifier having programmable operational characteristics and a serial communications interface are fabricated on an integrated circuit (IC). The serial communications interface controls the operational characteristics, e.g., gain, frequency response, etc., of the amplifier. A multiplexer (MUX) may also be included on the IC and may be controlled by the serial communications interface. Status of the amplifier may also be obtained through the serial communications interface. The pin count of the IC package may be kept to a minimum by using the serial communications interface.