Abstract: The present invention provides a semiconductor integrated circuit comprising a plurality of logic circuits, each of which has at least a first field effect transistor with a first gate connected to a high voltage line and at least a second field effect transistor with a second gate connected to a ground line, wherein said first gates of said plurality of logic circuits are commonly connected through a first interconnection structure to a first resistance which is connected to said high voltage line and wherein said second gates of said plurality of logic circuits are also commonly connected through a second interconnection structure to a second resistance which is connected to said ground line. The first and second interconnection structures enable the single first resistance and the single second resistance to prevent the gate breakdown of the gates in the plurality of the logic circuits.