Abstract: A delivery server includes a processor including hardware, the processor being configured to: transmit arrival information of a product to a user terminal carried by a user who has ordered the product; transmit, in a case where unattended delivery is instructed by the user terminal, unattended delivery information to a home delivery terminal of a delivery person who delivers the product, and request a signature of the user; transmit the signature information to the home delivery terminal in response to receiving signature information regarding the signature of the user from the user terminal; and transmit delivery completion information of the product to the user terminal.

Abstract: Devices are disclosed. A device may include a command and address (CA) interface including a first pair of input circuits arranged in a first direction. The CA interface further including at least one additional pair of input circuits arranged in a second direction relative to the first pair of input circuits. Associated systems are also disclosed.

Abstract: Devices are disclosed. A device may include an interface region including two or more input circuits operably coupled to the number of input signals, wherein one of the two or more input circuits for each input signal is adjacent at least two other input circuits coupled to different input. Associated systems are also disclosed.

Abstract: Disclosed herein is an apparatus that includes: first and second wiring patterns extending in a first direction, first and second transistors arranged adjacent to each other, and third to sixth wiring patterns extending in a second direction. The third wiring pattern is connected between the first wiring pattern and one of source/drain regions of the first transistor, the fourth wiring pattern is connected between the second wiring pattern and other of source/drain regions of the first transistor, the fifth wiring pattern is connected to one of source/drain regions of the second transistor, the fifth wiring pattern overlapping with the first wiring pattern, the sixth wiring pattern is connected to other of source/drain regions of the second transistor, the sixth wiring pattern overlapping with the second wiring pattern. The third and fourth wiring patterns are greater in width in the first direction than the fifth and sixth wiring patterns.

Abstract: Disclosed herein is an apparatus that includes: first and second wiring patterns extending in a first direction, first and second transistors arranged adjacent to each other, and third to sixth wiring patterns extending in a second direction. The third wiring pattern is connected between the first wiring pattern and one of source/drain regions of the first transistor, the fourth wiring pattern is connected between the second wiring pattern and other of source/drain regions of the first transistor, the fifth wiring pattern is connected to one of source/drain regions of the second transistor, the fifth wiring pattern overlapping with the first wiring pattern, the sixth wiring pattern is connected to other of source/drain regions of the second transistor, the sixth wiring pattern overlapping with the second wiring pattern. The third and fourth wiring patterns are greater in width in the first direction than the fifth and sixth wiring patterns.

Abstract: Devices are disclosed. A device may include an interface region including two or more input circuits operably coupled to the number of input signals, wherein one of the two or more input circuits for each input signal is adjacent at least two other input circuits coupled to different input. Associated systems are also disclosed.

Abstract: Disclosed herein is an apparatus that includes: first and second wiring patterns extending in a first direction, first and second transistors arranged adjacent to each other, and third to sixth wiring patterns extending in a second direction. The third wiring pattern is connected between the first wiring pattern and one of source/drain regions of the first transistor, the fourth wiring pattern is connected between the second wiring pattern and other of source/drain regions of the first transistor, the fifth wiring pattern is connected to one of source/drain regions of the second transistor, the fifth wiring pattern overlapping with the first wiring pattern, the sixth wiring pattern is connected to other of source/drain regions of the second transistor, the sixth wiring pattern overlapping with the second wiring pattern. The third and fourth wiring patterns are greater in width in the first direction than the fifth and sixth wiring patterns.

Abstract: Memory devices, memory systems, and systems, include memory devices with a bonding pad region including two or more bonding pads for operably coupling to external signals and a number of command-and-address (CA) input signals. The memory device also includes a centralized CA interface region including two or more CA input circuits operably coupled to the number of input signals. One of the two or more CA input circuits for each CA input signal may border at least two other CA input circuits coupled to different CA input signals.

Abstract: Disclosed herein is an apparatus that includes: first and second wiring patterns extending in a first direction, first and second transistors arranged adjacent to each other, and third to sixth wiring patterns extending in a second direction. The third wiring pattern is connected between the first wiring pattern and one of source/drain regions of the first transistor, the fourth wiring pattern is connected between the second wiring pattern and other of source/drain regions of the first transistor, the fifth wiring pattern is connected to one of source/drain regions of the second transistor, the fifth wiring pattern overlapping with the first wiring pattern, the sixth wiring pattern is connected to other of source/drain regions of the second transistor, the sixth wiring pattern overlapping with the second wiring pattern. The third and fourth wiring patterns are greater in width in the first direction than the fifth and sixth wiring patterns.

Abstract: Memory devices, memory systems, and systems, include memory devices with a bonding pad region including two or more bonding pads for operably coupling to external signals and a number of command-and-address (CA) input signals. The memory device also includes centralized CA interface region including two or more CA input circuits operably coupled to the number of input signals. One of the tow or more CA input circuits for each CA input signal may border at least two other CA input circuits coupled to different CA input signals.

Abstract: Memory devices, memory systems, and systems, include memory devices with a bonding pad region including two or more bonding pads for operably coupling to external signals and two or more command-and-address (CA) input signals. The memory device also includes a memory cell region for storing information in a plurality of memory cells. A centralized CA interface region including two or more CA input circuits operably coupled to the two or more CA input signals. The centralized CA interface region is positioned between the bonding pad region and the memory cell region in a layout arrangement with the two or more CA input circuits neighboring each other in a compact region such that clock routing to the two or more CA input circuits is substantially reduced.

Abstract: Memory devices, memory systems, and systems, include memory devices with a bonding pad region including two or more bonding pads for operably coupling to external signals and two or more command-and-address (CA) input signals. The memory device also includes a memory cell region for storing information in a plurality of memory cells. A centralized CA interface region including two or more CA input circuits operably coupled to the two or more CA input signals. The centralized CA interface region is positioned between the bonding pad region and the memory cell region in a layout arrangement with the two or more CA input circuits neighboring each other in a compact region such that clock routing to the two or more CA input circuits is substantially reduced.

Abstract: In order to provide an information providing system appropriate for acquiring information associated with text contained in a Web document, a plugin program is executed in a client device, and settings in a dispatch unit are modified. Specification of text in a Web document by an input reception unit, acquisition of text from the Internet by a document acquisition unit, and display on a screen by a document display unit are hooked when required. When a first type instruction specifying a URL is input with the input reception unit, a document is acquired by a document acquisition unit. When a second type instruction is input, an associated information acquisition unit queries a plurality of server devices with the text, and an associated information display unit displays the associated information provided in a popup.

Abstract: In order to provide an information providing system appropriate for acquiring information associated with text contained in a Web document, a plugin program is executed in a client device (301), and settings in a dispatch unit (305) are modified. Specification of text in a Web document by an input reception unit (304), acquisition of text from the Internet by a document acquisition unit (302), and display on a screen by a document display unit (303) are hooked when required. When a first type instruction specifying a URL is input with the input reception unit (304), a document is acquired by a document acquisition unit (302). When a second type instruction is input, an associated information acquisition unit (811) queries a plurality of server devices with the text, and an associated information display unit (812) displays the associated information provided in a popup.

Abstract: This invention relates to a polyvinyl alcohol type polarizing film or plate which comprises a water-soluble dye having the formula (1) in a free acid form or a copper complex salt thereof.

Abstract: This invention relates to a polyvinyl alcohol type polarizing film or plate which comprises a water-soluble dye having the formula (1) in a free acid form or a copper complex salt thereof. The said polarizing plate has excellent polarizing performance capability and durability, and is suitably used for the green channel of a liquid crystal projector when B in formula (1) is a benzoylamino group and the water-soluble dye has a wave length for maximum absorption (?max) of 520 nm or more and less than 580 nm.

Abstract: This invention relates to a polyvinyl alcohol type polarizing film or plate which comprises a water-soluble dye having the formula (1) in a free acid form or a copper complex salt thereof. The said polarizing plate has excellent polarizing performance capability and durability, and is suitably used for the green channel of a liquid crystal projector when B in formula (1) is a benzoylamino group and the water-soluble dye has a wavelength for maximum absorption (&lgr;max) of 520 nm or more and less than 580 nm.