Patents by Inventor Kumiko Mito

Kumiko Mito has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7492650
    Abstract: The present invention provides a semiconductor storage device that requires no specialized circuit or the like for reading redundancy data from a redundancy region, and that is capable of freely changing the arrangement of the redundancy region in the memory array area. A semiconductor storage device of the present invention includes a memory array configured as shown below. The memory array includes a user region which is composed of given page units and where user data is stored, and a redundancy region which is composed of the same given page units and where redundancy data is stored. The area in the memory array can be used either as the user region or as the redundancy region.
    Type: Grant
    Filed: December 20, 2006
    Date of Patent: February 17, 2009
    Assignee: MegaChips LSI Solutions Inc.
    Inventors: Kumiko Mito, Takashi Oshikiri
  • Patent number: 7366860
    Abstract: A storage device is capable of sequentially inputting a command, which includes address information and attached information, from an information processor through an input/output unit. The storage device includes a storage unit for storing data; an extractor for extracting the address information and the attached information from an input command inputted through the input/output unit; a generator for, in response to input of the input command, generating transition information that transitions according to rules using an initial value; a comparator for determining whether the attached information and the transition information agree with each other; and an output controller for, only when the attached information and the transition information agree with each other, outputting storage data out of the data, which corresponds to the address information extracted by the extractor, through the input/output unit.
    Type: Grant
    Filed: November 2, 2005
    Date of Patent: April 29, 2008
    Inventor: Kumiko Mito
  • Publication number: 20080019518
    Abstract: A semiconductor memory includes a memory array and a scramble/descramble unit. The scramble/descramble unit scrambles read data read from the memory array to generate output data, and descrambles a received scrambled signal to generate a command for the memory array. The scramble/descramble unit updates a method of generating keys used for scrambling/descrambling when one selected between at least two out of the scrambled signal, the command, the read data, and the output data satisfies prescribed conditions, respectively.
    Type: Application
    Filed: June 12, 2007
    Publication date: January 24, 2008
    Applicant: MegaChips Corporation
    Inventor: Kumiko MITO
  • Publication number: 20070171710
    Abstract: A memory cell array includes a memory cell transistor storing data of a value in accordance with a set threshold voltage. A writing control unit controls writing of data in the memory cell transistor. A memory cell driving unit writes data in the memory cell transistor under the control of the writing control unit. The writing control unit is capable of setting at least three types of threshold voltages having different values for the memory cell transistor by controlling the memory cell driving unit, and uses only a plurality types of threshold voltages having values not adjacent to each other of the at least three types of threshold voltages in writing data in the memory cell transistor.
    Type: Application
    Filed: December 21, 2006
    Publication date: July 26, 2007
    Applicant: MegaChips LSI Solutions Inc.
    Inventors: Kumiko MITO, Takashi Oshikiri
  • Publication number: 20070171737
    Abstract: The present invention provides a semiconductor storage device that requires no specialized circuit or the like for reading redundancy data from a redundancy region, and that is capable of freely changing the arrangement of the redundancy region in the memory array area. A semiconductor storage device of the present invention includes a memory array configured as shown below. The memory array includes a user region which is composed of given page units and where user data is stored, and a redundancy region which is composed of the same given page units and where redundancy data is stored. The area in the memory array can be used either as the user region or as the redundancy region.
    Type: Application
    Filed: December 20, 2006
    Publication date: July 26, 2007
    Applicant: MegaChips LSI Solutions Inc.
    Inventors: Kumiko Mito, Takashi Oshikiri
  • Publication number: 20060109730
    Abstract: A storage device is capable of sequentially inputting a command, which includes address information and attached information, from an information processor through an input/output unit. The storage device includes a storage unit for storing data; an extractor for extracting the address information and the attached information from an input command inputted through the input/output unit; a generator for, in response to input of the input command, generating transition information that transitions according to rules using an initial value; a comparator for determining whether the attached information and the transition information agree with each other; and an output controller for, only when the attached information and the transition information agree with each other, outputting storage data out of the data, which corresponds to the address information extracted by the extractor, through the input/output unit.
    Type: Application
    Filed: November 2, 2005
    Publication date: May 25, 2006
    Inventor: Kumiko Mito