Patents by Inventor Kun-A Kang
Kun-A Kang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 7205658Abstract: A singulation method used in leadless packaging process is disclosed. An array of molded products on an upper surface of a lead frame is utilized in the singulation method. The lead frame has a plurality of dambars between the molded products. The lower surface of the lead frame is attached with a tape. Each of the molded products includes a semiconductor chip encapsulated in a package body and electrically coupled to the upper surface of the lead frame. The singulation method is accomplished by etching the upper surface of the lead frame with the package bodies as mask until each dambar is etched away.Type: GrantFiled: June 29, 2004Date of Patent: April 17, 2007Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Jun Hong Lee, Hyung Jun Park, Hyeong No Kim, Kun A Kang
-
Patent number: 6861295Abstract: A low-pin-count chip package including a die pad for receiving a semiconductor chip and a plurality of connection pads electrically coupled to the semiconductor chip. The semiconductor chip, the die pad, and the connection pads are encapsulated in a package body such that the lower surfaces of the die pad and the connection pads are exposed through the package body. The present invention is characterized in that the die pad and the connection pads have a substantially concave profile thereby prolonging the time for moisture diffusion into the package as well as enhancing the “locking” of the die pad and the connection pads in the package body. The present invention further provides a method of producing the low-pin-count chip package described above.Type: GrantFiled: December 19, 2001Date of Patent: March 1, 2005Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Kyujin Jung, Kun-A Kang, Hyung Jun Park
-
Patent number: 6773961Abstract: A singulation method used in leadless packaging process is disclosed. An array of molded products on an upper surface of a lead frame is utilized in the singulation method. The lead frame has a plurality of dambars between the molded products. The lower surface of the lead frame is attached with a tape. Each of the molded products includes a semiconductor chip encapsulated in a package body and electrically coupled to the upper surface of the lead frame. The singulation method is accomplished by etching the upper surface of the lead frame with the package bodies as mask until each dambar is etched away.Type: GrantFiled: August 15, 2003Date of Patent: August 10, 2004Assignee: Advanced Semiconductor Engineering INC.Inventors: Jun Hong Lee, Hyung Jun Park, Hyeong No Kim, Kun A Kang
-
Patent number: 6528893Abstract: A low-pin-count chip package including a die pad for receiving a semiconductor chip and a plurality of connection pads electrically coupled to the semiconductor chip. The semiconductor chip, the die pad, and the connection pads are encapsulated in a package body such that the lower surfaces of the die pad and the connection pads are exposed through the package body. The present invention is characterized in that the die pad and the connection pads are formed by etching such that they have a concave profile and a thickness far larger than that of conventional die pad and connection pads formed by plating. This prolongs the path and time for moisture diffusion into the package, and significantly increases the area of the interface between the package body and the die pad as well as the connection pads thereby promoting adhesion therebetween. The present invention further provides a method of producing the low-pin-count chip package described above.Type: GrantFiled: June 7, 2001Date of Patent: March 4, 2003Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Kyujin Jung, Kun-A Kang
-
Publication number: 20020197826Abstract: A singulation method comprising: (a) providing a molded product including semiconductor chips attached and electrically coupled to an upper surface of a lead frame wherein a lower surface of the lead frame is exposed from the bottom of the molded product, the lead frame including a plurality of units in an array arrangement and cutting streets between the units, each unit having a die pad and leads arranged at the periphery of the die pad, a first metal layer formed on the entire lower surface of the lead frame except the cutting streets; (b) etching the lower surface of the lead frame with the first metal layer as mask such that the cutting streets are etched away to form a plurality of grooves; and (c) cutting the etched molded product along the grooves to obtain the leadless semiconductor packages.Type: ApplicationFiled: August 14, 2001Publication date: December 26, 2002Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Hyeongno Kim, Hyung Jun Park, Sangbae Park, Junhong Lee, Kun-A Kang, Bae Doo Kim
-
Patent number: 6495909Abstract: A low-pin-count chip package including a die pad for receiving a semiconductor chip and a plurality of connection pads electrically coupled to the semiconductor chip. The semiconductor chip, the die pad, and the connection pads are encapsulated by a package body in a manner that the lower surfaces of the die pad and the connection pads are exposed through the package body. The present invention is characterized in that the die pad and the connection pads have a T-shaped profile thereby prolonging the time for moisture diffusion into the package as well as enhancing the “locking” of the die pad and the connection pads in the package body. The present invention further provides a method of producing the low-pin-count chip package described above.Type: GrantFiled: August 30, 2001Date of Patent: December 17, 2002Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Kyujin Jung, Kun-A Kang
-
Patent number: 6489218Abstract: A singulation method comprising: (a) providing a molded product including semiconductor chips attached and electrically coupled to an upper surface of a lead frame wherein a lower surface of the lead frame is exposed from the bottom of the molded product, the lead frame including a plurality of units in an array arrangement and cutting streets between the units, each unit having a die pad and leads arranged at the periphery of the die pad, a first metal layer formed on the entire lower surface of the lead frame except the cutting streets; (b) etching the lower surface of the lead frame with the first metal layer as mask such that the cutting streets are etched away to form a plurality of grooves; and (c) cutting the etched molded product along the grooves to obtain the leadless semiconductor packages.Type: GrantFiled: August 14, 2001Date of Patent: December 3, 2002Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Hyeongno Kim, Hyung Jun Park, Sangbae Park, Junhong Lee, Kun-A Kang, Bae Doo Kim
-
Publication number: 20020056926Abstract: A low-pin-count chip package including a die pad for receiving a semiconductor chip and a plurality of connection pads electrically coupled to the semiconductor chip. The semiconductor chip, the die pad, and the connection pads are encapsulated in a package body such that the lower surfaces of the die pad and the connection pads are exposed through the package body. The present invention is characterized in that the die pad and the connection pads have a substantially concave profile thereby prolonging the time for moisture diffusion into the package as well as enhancing the “locking” of the die pad and the connection pads in the package body. The present invention further provides a method of producing the low-pin-count chip package described above.Type: ApplicationFiled: December 19, 2001Publication date: May 16, 2002Applicant: Advanced Semiconductor Engineering, Inc. Taiwan, R.O.C.Inventors: Kyujin Jung, Kun-A kang, Hyung Jun Park
-
Patent number: 6355502Abstract: A method for making a semiconductor package firstly provides a lead frame having a first surface and a corresponding second surface. The lead frame includes at least a package unit that further includes a die pad, and a plurality of leads disposed on the periphery of the die pad where each of the leads further includes a neck portion. The method then attaches the second surface of the lead frame to a tape, and performs a punching process to cut off the neck portion of the lead so as to form a plurality of conductive blocks disposed independently on the periphery of the die pad. The method further provides a chip having its back surface attach to the first surface of the die pad, and provides electrical connection between the bonding pad and the first surface of the conductive block by using a plurality of bonding wires. Further, the method performs an encapsulating process to encapsulate the chip, the bonding wires, the die pad, and the first surface of the conductive block.Type: GrantFiled: April 25, 2000Date of Patent: March 12, 2002Assignee: National Science CouncilInventors: Kun-A Kang, Hyung J. Park, J. H. Lee
-
Publication number: 20020024147Abstract: A low-pin-count chip package including a die pad for receiving a semiconductor chip and a plurality of connection pads electrically coupled to the semiconductor chip. The semiconductor chip, the die pad, and the connection pads are encapsulated by a package body in a manner that the lower surfaces of the die pad and the connection pads are exposed through the package body. The present invention is characterized in that the die pad and the connection pads have a T-shaped profile thereby prolonging the time for moisture diffusion into the package as well as enhancing the “locking” of the die pad and the connection pads in the package body. The present invention further provides a method of producing the low-pin-count chip package described above.Type: ApplicationFiled: August 30, 2001Publication date: February 28, 2002Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Kyujin Jung, Kun-A Kang
-
Patent number: 6342730Abstract: A low-pin-count chip package including a die pad for receiving a semiconductor chip and a plurality of connection pads electrically coupled to the semiconductor chip. The semiconductor chip, the die pad, and the connection pads are encapsulated in a package body such that the lower surfaces of the die pad and the connection pads are exposed through the package body. The present invention is characterized in that the die pad and the connection pads have a substantially concave profile thereby prolonging the time for moisture diffusion into the package as well as enhancing the “locking” of the die pad and the connection pads in the package body. The present invention further provides a method of producing the low-pin-count chip package described above.Type: GrantFiled: January 28, 2000Date of Patent: January 29, 2002Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Kyujin Jung, Kun-A Kang, Hyung Jun Park
-
Patent number: 6333252Abstract: A low-pin-count chip package including a die pad for receiving a semiconductor chip and a plurality of connection pads electrically coupled to the semiconductor chip. The semiconductor chip, the die pad, and the connection pads are encapsulated by a package body in a manner that the lower surfaces of the die pad and the connection pads are exposed through the package body. The present invention is characterized in that the die pad and the connection pads have a T-shaped profile thereby prolonging the time for moisture diffusion into the package as well as enhancing the “locking” of the die pad and the connection pads in the package body. The present invention further provides a method of producing the low-pin-count chip package described above.Type: GrantFiled: January 5, 2000Date of Patent: December 25, 2001Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Kyujin Jung, Kun-A Kang
-
Publication number: 20010049156Abstract: A low-pin-count chip package including a die pad for receiving a semiconductor chip and a plurality of connection pads electrically coupled to the semiconductor chip. The semiconductor chip, the die pad, and the connection pads are encapsulated in a package body such that the lower surfaces of the die pad and the connection pads are exposed through the package body. The present invention is characterized in that the die pad and the connection pads are formed by etching such that they have a concave profile and a thickness far larger than that of conventional die pad and connection pads formed by plating. This prolongs the path and time for moisture diffusion into the package, and significantly increases the area of the interface between the package body and the die pad as well as the connection pads thereby promoting adhesion therebetween. The present invention further provides a method of producing the low-pin-count chip package described above.Type: ApplicationFiled: June 7, 2001Publication date: December 6, 2001Applicant: ADVANCED SEMICONDUCTO ENGINEERING, INC.Inventors: Kyujin Jung, Kun-A Kang
-
Patent number: 6261864Abstract: A low-pin-count chip package including a die pad for receiving a semiconductor chip and a plurality of connection pads electrically coupled to the semiconductor chip. The semiconductor chip, the die pad, and the connection pads are encapsulated in a package body such that the lower surfaces of the die pad and the connection pads are exposed through the package body. The present invention is characterized in that the die pad and the connection pads are formed by etching such that they have a concave profile and a thickness far larger than that of conventional die pad and connection pads formed by plating. This prolongs the path and time for moisture diffusion into the package, and significantly increases the area of the interface between the package body and the die pad as well as the connection pads thereby promoting adhesion therebetween. The present invention further provides a method of producing the low-pin-count chip package described above.Type: GrantFiled: January 28, 2000Date of Patent: July 17, 2001Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Kyujin Jung, Kun-A Kang
-
Patent number: 6242284Abstract: A method for packaging a semiconductor chip, generally comprising the following steps of: (a) forming a plurality of openings on the top surface of the conducting substrate, wherein the upper portions of the openings are formed larger than the lower portions of the openings; (b) forming insulating sections in the conducting substrate by filling an insulating material in the openings; (c) forming a plurality of leads insulated by the insulating sections by planarizing the bottom surface of the conducting substrate to expose and form planarized bottom surfaces of the insulating sections; (d) mounting a semiconductor chip on the bottom surface of the conducting substrate; (e) providing a plurality of conducting wires to electrically connect the semiconductor chip to the leads; and (f) encapsulating the semiconductor chip and the conducting wires.Type: GrantFiled: May 5, 2000Date of Patent: June 5, 2001Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Kun-A Kang, Kyujin Jung, Hyung Jun Park, Jun Hong Lee