Patents by Inventor Kun Bao
Kun Bao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12223408Abstract: Provided is a system and method for training and validating models in a machine learning pipeline for failure mode analytics. The machine learning pipeline may include an unsupervised training phase, a validation phase and a supervised training and scoring phase. In one example, the method may include receiving an identification of a machine learning model, executing a machine learning pipeline comprising a plurality of services which train the machine learning model via at least one of an unsupervised learning process and a supervised learning process, the machine learning pipeline being controlled by an orchestration module that triggers ordered execution of the services, and storing the trained machine learning model output from the machine learning pipeline in a database associated with the machine learning pipeline.Type: GrantFiled: February 20, 2023Date of Patent: February 11, 2025Assignee: SAP SEInventors: Lukas Carullo, Patrick Brose, Kun Bao, Anubhav Bhatia, Leonard Brzezinski, Lauren McMullen, Simon Lee
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Publication number: 20250031366Abstract: A semiconductor structure is disclosed. The semiconductor structure includes a staircase structure disposed over a substrate. The staircase structure includes a plurality of layer stacks, where each layer stack is made of a first material layer over a portion of a second material layer. The staircase structure further includes a plurality of landing pads, where each landing pad is disposed over another portion of the second material layer of a respective layer stack.Type: ApplicationFiled: October 4, 2024Publication date: January 23, 2025Applicant: Yangtze Memory Technologies Co., Ltd.Inventors: Zhenyu LU, Jun CHEN, Xiaowang DAI, Jifeng ZHU, Qian TAO, Yu Ru HUANG, Si Ping HU, Lan YAO, Li Hong XIAO, A Man ZHENG, Kun BAO, Haohao YANG
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Patent number: 12137558Abstract: A semiconductor structure is disclosed. The semiconductor structure includes a staircase structure disposed over a substrate. The staircase structure includes a plurality of layer stacks, where each layer stack is made of a first material layer over a portion of a second material layer. The staircase structure further includes a plurality of landing pads, where each landing pad is disposed over another portion of the second material layer of a respective layer stack.Type: GrantFiled: November 10, 2022Date of Patent: November 5, 2024Assignee: Yangtze Memory Technologies Co., Ltd.Inventors: Zhenyu Lu, Jun Chen, Xiaowang Dai, Jifeng Zhu, Qian Tao, Yu Ru Huang, Si Ping Hu, Lan Yao, Li Hong Xiao, A Man Zheng, Kun Bao, Haohao Yang
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Patent number: 12055902Abstract: Provided is a system and method for training and validating models in a machine learning pipeline for failure mode analytics. The machine learning pipeline may include an unsupervised training phase, a validation phase and a supervised training and scoring phase. In one example, the method may include receiving a request to create a machine learning model for failure mode detection associated with an asset, retrieving historical notification data of the asset, generating an unsupervised machine learning model via unsupervised learning on the historical notification data, wherein the unsupervised learning comprises identifying failure topics from text included in the historical notification data and mapping the identified failure topics to a plurality of predefined failure modes for the asset, and storing the generated unsupervised machine learning model via a storage device.Type: GrantFiled: January 12, 2023Date of Patent: August 6, 2024Assignee: SAP SEInventors: Lukas Carullo, Patrick Brose, Kun Bao, Anubhav Bhatia, Rashmi Shetty B, Leonard Brzezinski, Lauren McMullen, Harpreet Singh, Karthik Mohan Mokashi, Simon Lee
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Patent number: 12010838Abstract: A semiconductor structure is disclosed. The semiconductor structure includes a staircase structure disposed over a substrate. The staircase structure includes a plurality of layer stacks, where each layer stack is made of a first material layer over a portion of a second material layer. The staircase structure further includes a plurality of landing pads, where each landing pad is disposed over another portion of the second material layer of a respective layer stack.Type: GrantFiled: September 13, 2021Date of Patent: June 11, 2024Assignee: Yangtze Memory Technologies Co., Ltd.Inventors: Zhenyu Lu, Jun Chen, Xiaowang Dai, Jifeng Zhu, Qian Tao, Yu Ru Huang, Si Ping Hu, Lan Yao, Li Hong Xiao, A Man Zheng, Kun Bao, Haohao Yang
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Publication number: 20240114687Abstract: Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a memory stack, a channel structure, a channel local contact, a slit structure, and a staircase local contact. The memory stack includes interleaved conductive layers and dielectric layers above the substrate. The channel structure extends vertically through the memory stack. The channel local contact is above and in contact with the channel structure. The slit structure extends vertically through the memory stack. The staircase local contact is above and in contact with one of the conductive layers at a staircase structure on an edge of the memory stack. Upper ends of the channel local contact, the slit structure, and the staircase local contact are flush with one another.Type: ApplicationFiled: December 13, 2023Publication date: April 4, 2024Inventors: Kun Zhang, Haojie Song, Kun Bao, Zhiliang Xia
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Patent number: 11910599Abstract: Embodiments of contact structures of a three-dimensional memory device and fabrication method thereof are disclosed. The three-dimensional memory structure includes a film stack disposed on a substrate, wherein the film stack includes a plurality of conductive and dielectric layer pairs, each conductive and dielectric layer pair having a conductive layer and a first dielectric layer. The three-dimensional memory structure also includes a staircase structure formed in the film stack, wherein the staircase structure includes a plurality of steps, each staircase step having two or more conductive and dielectric layer pairs. The three-dimensional memory structure further includes a plurality of coaxial contact structures formed in a first insulating layer over the staircase structure, wherein each coaxial contact structure includes one or more conductive and insulating ring pairs and a conductive core, each conductive and insulating ring pair having a conductive ring and an insulating ring.Type: GrantFiled: November 23, 2022Date of Patent: February 20, 2024Assignee: Yangtze Memory Technologies Co., Ltd.Inventors: Zhongwang Sun, Guangji Li, Kun Zhang, Ming Hu, Jiwei Cheng, Shijin Luo, Kun Bao, Zhiliang Xia
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Patent number: 11903204Abstract: Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a memory stack, a channel structure, a channel local contact, a slit structure, and a staircase local contact. The memory stack includes interleaved conductive layers and dielectric layers above the substrate. The channel structure extends vertically through the memory stack. The channel local contact is above and in contact with the channel structure. The slit structure extends vertically through the memory stack. The staircase local contact is above and in contact with one of the conductive layers at a staircase structure on an edge of the memory stack. Upper ends of the channel local contact, the slit structure, and the staircase local contact are flush with one another.Type: GrantFiled: April 25, 2022Date of Patent: February 13, 2024Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.Inventors: Kun Zhang, Haojie Song, Kun Bao, Zhiliang Xia
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Publication number: 20230206137Abstract: Provided is a system and method for training and validating models in a machine learning pipeline for failure mode analytics. The machine learning pipeline may include an unsupervised training phase, a validation phase and a supervised training and scoring phase. In one example, the method may include receiving an identification of a machine learning model, executing a machine learning pipeline comprising a plurality of services which train the machine learning model via at least one of an unsupervised learning process and a supervised learning process, the machine learning pipeline being controlled by an orchestration module that triggers ordered execution of the services, and storing the trained machine learning model output from the machine learning pipeline in a database associated with the machine learning pipeline.Type: ApplicationFiled: February 20, 2023Publication date: June 29, 2023Inventors: Lukas Carullo, Patrick Brose, Kun Bao, Anubhav Bhatia, Leonard Brzezinski, Lauren McMullen, Simon Lee
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Publication number: 20230197532Abstract: Aspects of the disclosure provide methods for determining wafer flatness and for fabricating a semiconductor device. The method includes storing a first wafer expansion of a first wafer that is collected along a first direction parallel to a working surface of the first wafer during a lithography process. The lithography process is for patterning structures on the working surface of the first wafer. Before a fabrication step with a wafer flatness requirement, a wafer flatness of the first wafer is determined based on the first wafer expansion collected during the lithography process using a flatness prediction model that is configured to predict the wafer flatness. In an example, a layer is deposited on a back side of the first wafer with a thickness that is based on the determined wafer flatness of the first wafer.Type: ApplicationFiled: July 28, 2022Publication date: June 22, 2023Applicant: Yangtze Memory Technologies Co., Ltd.Inventors: Xin LEI, Ying CHOU, HaoJie SONG, Kun BAO, Fan WANG, Guoxiu JIN
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Publication number: 20230168639Abstract: Provided is a system and method for training and validating models in a machine learning pipeline for failure mode analytics. The machine learning pipeline may include an unsupervised training phase, a validation phase and a supervised training and scoring phase. In one example, the method may include receiving a request to create a machine learning model for failure mode detection associated with an asset, retrieving historical notification data of the asset, generating an unsupervised machine learning model via unsupervised learning on the historical notification data, wherein the unsupervised learning comprises identifying failure topics from text included in the historical notification data and mapping the identified failure topics to a plurality of predefined failure modes for the asset, and storing the generated unsupervised machine learning model via a storage device.Type: ApplicationFiled: January 12, 2023Publication date: June 1, 2023Inventors: Lukas Carullo, Patrick Brose, Kun Bao, Anubhav Bhatia, Rashmi Shetty B, Leonard Brzezinski, Lauren McMullen, Harpreet Singh, Karthik Mohan Mokashi, Simon Lee
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Publication number: 20230142924Abstract: A method for forming a 3D NAND memory device is provided. The method includes: providing a semiconductor structure including a semiconductor substrate, a stacked structure, and a dielectric layer covering the semiconductor substrate and the stacked structure; forming, in the dielectric layer and the stacked structure, channel through vias penetrating through the stacked structure; forming a channel structure in each channel through via, and sequentially forming a polysilicon layer, a first metal silicide layer located on the polysilicon layer, and a through via contact metal layer located on the first metal silicide layer in the channel structure; forming a first through via in the dielectric layer for exposing the semiconductor substrate after forming the first metal silicide layer; forming a second metal silicide layer at a bottom of the first through via; and forming a first contact plug connected to the second metal silicide layer in the first through via.Type: ApplicationFiled: December 28, 2022Publication date: May 11, 2023Inventors: Haojie Song, Qian Gao, Kun Bao, Huan He, Yajun Huang, Yansan Ma
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Publication number: 20230086425Abstract: Embodiments of contact structures of a three-dimensional memory device and fabrication method thereof are disclosed. The three-dimensional memory structure includes a film stack disposed on a substrate, wherein the film stack includes a plurality of conductive and dielectric layer pairs, each conductive and dielectric layer pair having a conductive layer and a first dielectric layer. The three-dimensional memory structure also includes a staircase structure formed in the film stack, wherein the staircase structure includes a plurality of steps, each staircase step having two or more conductive and dielectric layer pairs. The three-dimensional memory structure further includes a plurality of coaxial contact structures formed in a first insulating layer over the staircase structure, wherein each coaxial contact structure includes one or more conductive and insulating ring pairs and a conductive core, each conductive and insulating ring pair having a conductive ring and an insulating ring.Type: ApplicationFiled: November 23, 2022Publication date: March 23, 2023Applicant: Yangtze Memory Technologies Co., Ltd.Inventors: Zhongwang SUN, Guangji LI, Kun ZHANG, Ming HU, Jiwei CHENG, Shijin LUO, Kun BAO, Zhiliang XIA
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Publication number: 20230084008Abstract: A semiconductor structure is disclosed. The semiconductor structure includes a staircase structure disposed over a substrate. The staircase structure includes a plurality of layer stacks, where each layer stack is made of a first material layer over a portion of a second material layer. The staircase structure further includes a plurality of landing pads, where each landing pad is disposed over another portion of the second material layer of a respective layer stack.Type: ApplicationFiled: September 13, 2021Publication date: March 16, 2023Applicant: Yangtze Memory Technologies Co., Ltd.Inventors: Zhenyu Lu, Jun Chen, Xiaowang Dai, Jifeng Zhu, Qian Tao, Yu Ru Huang, Si Ping Hu, Lan Yao, Li Hong Xiao, A Man Zheng, Kun Bao, Haohao Yang
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Publication number: 20230083030Abstract: A semiconductor structure is disclosed. The semiconductor structure includes a staircase structure disposed over a substrate. The staircase structure includes a plurality of layer stacks, where each layer stack is made of a first material layer over a portion of a second material layer. The staircase structure further includes a plurality of landing pads, where each landing pad is disposed over another portion of the second material layer of a respective layer stack.Type: ApplicationFiled: November 10, 2022Publication date: March 16, 2023Applicant: Yangtze Memory Technologies Co., Ltd.Inventors: Zhenyu Lu, Jun Chen, Xiaowang Dai, Jifeng Zhu, Qian Tao, Yu Ru Huang, Si Ping Hu, Lan Yao, Li Hong Xiao, A Man Zheng, Kun Bao, Haohao Yang
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Patent number: 11586986Abstract: Provided is a system and method for training and validating models in a machine learning pipeline for failure mode analytics. The machine learning pipeline may include an unsupervised training phase, a validation phase and a supervised training and scoring phase. In one example, the method may include receiving an identification of a machine learning model, executing a machine learning pipeline comprising a plurality of services which train the machine learning model via at least one of an unsupervised learning process and a supervised learning process, the machine learning pipeline being controlled by an orchestration module that triggers ordered execution of the services, and storing the trained machine learning model output from the machine learning pipeline in a database associated with the machine learning pipeline.Type: GrantFiled: February 25, 2019Date of Patent: February 21, 2023Assignee: SAP SEInventors: Lukas Carullo, Patrick Brose, Kun Bao, Anubhav Bhatia, Leonard Brzezinski, Lauren McMullen, Simon Lee
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Patent number: 11574925Abstract: A memory stack including interleaved conductive layers and dielectric layers is formed by replacing, through a slit opening, sacrificial layers with conductive layers. A first source contact portion is formed in the slit opening. Simultaneously, a channel local contact opening is formed through a local dielectric layer to expose a channel structure, and a staircase local contact opening is formed through the local dielectric layer to expose one of the conductive layers at a staircase structure on an edge of the memory stack. Also, simultaneously, a channel local contact, a second source contact portion above a first source contact portion in the slit opening, and a staircase local contact are formed, respectively, in the channel local contact opening, the slit opening, and the staircase local contact opening.Type: GrantFiled: April 12, 2021Date of Patent: February 7, 2023Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.Inventors: Kun Zhang, Haojie Song, Kun Bao, Zhiliang Xia
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Patent number: 11567460Abstract: Provided is a system and method for training and validating models in a machine learning pipeline for failure mode analytics. The machine learning pipeline may include an unsupervised training phase, a validation phase and a supervised training and scoring phase. In one example, the method may include receiving a request to create a machine learning model for failure mode detection associated with an asset, retrieving historical notification data of the asset, generating an unsupervised machine learning model via unsupervised learning on the historical notification data, wherein the unsupervised learning comprises identifying failure topics from text included in the historical notification data and mapping the identified failure topics to a plurality of predefined failure modes for the asset, and storing the generated unsupervised machine learning model via a storage device.Type: GrantFiled: February 25, 2019Date of Patent: January 31, 2023Assignee: SAP SEInventors: Lukas Carullo, Patrick Brose, Kun Bao, Anubhav Bhatia, Rashmi Shetty B, Leonard Brzezinski, Lauren McMullen, Harpreet Singh, Karthik Mohan Mokashi, Simon Lee
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Patent number: 11552091Abstract: Embodiments of contact structures of a three-dimensional memory device and fabrication method thereof are disclosed. The three-dimensional memory structure includes a film stack disposed on a substrate, wherein the film stack includes a plurality of conductive and dielectric layer pairs, each conductive and dielectric layer pair having a conductive layer and a first dielectric layer. The three-dimensional memory structure also includes a staircase structure formed in the film stack, wherein the staircase structure includes a plurality of steps, each staircase step having two or more conductive and dielectric layer pairs. The three-dimensional memory structure further includes a plurality of coaxial contact structures formed in a first insulating layer over the staircase structure, wherein each coaxial contact structure includes one or more conductive and insulating ring pairs and a conductive core, each conductive and insulating ring pair having a conductive ring and an insulating ring.Type: GrantFiled: May 6, 2021Date of Patent: January 10, 2023Assignee: Yangtze Memory Technologies Co., Ltd.Inventors: Zhongwang Sun, Guangji Li, Kun Zhang, Ming Hu, Jiwei Cheng, Shijin Luo, Kun Bao, Zhiliang Xia
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Patent number: D989293Type: GrantFiled: April 22, 2021Date of Patent: June 13, 2023Inventor: Kun Bao