Patents by Inventor Kun Chang

Kun Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240145379
    Abstract: Methods and semiconductor devices are provided. A method includes determining a location of a polyimide opening (PIO) corresponding to an under-bump metallization (UBM) feature in a die. The die includes a substrate and an interconnect structure over the substrate. The method also includes determining a location of a stacked via structure in the interconnect structure based on the location of the PIO. The method further includes forming, in the interconnect structure, the stacked via structure comprising at most three stacked contact vias at the location of the PIO.
    Type: Application
    Filed: February 23, 2023
    Publication date: May 2, 2024
    Inventors: Yen-Kun Lai, Wei-Hsiang Tu, Ching-Ho Cheng, Cheng-Nan Lin, Chiang-Jui Chu, Chien Hao Hsu, Kuo-Chin Chang, Mirng-Ji Lii
  • Publication number: 20240132904
    Abstract: The present invention relates to a method for producing recombinant human prethrombin-2 protein and having human ?-thrombin activity by the plant-based expression systems.
    Type: Application
    Filed: October 16, 2023
    Publication date: April 25, 2024
    Applicant: PROVIEW-MBD BIOTECH CO., LTD.
    Inventors: Yu-Chia CHANG, Jer-Cheng KUO, Ruey-Chih SU, Li-Kun HUANG, Ya-Yun LIAO, Ching-I LEE, Shao-Kang HUNG
  • Publication number: 20240136929
    Abstract: A buck converter includes a high-side N-FET, a low-side N-FET, a P-FET, a between a gate terminal and a source terminal of the P-FET, aa capacitor, and a FET driver. The FET driver operates in a selectable one of a continuous current mode and a discontinuous current mode. In a first phase of the discontinuous current mode, a gate voltage on the gate terminal the N-FET equalizes to a source voltage on the source terminal of the N-FET to turn on the first N-FET. A high output voltage on a high-side output of the FET driver is high enough to overcome a threshold voltage of a body diode of the first P-FET to provide the high output voltage minus a threshold voltage to the gate terminal of the high-side P-FET to turn on the high-side P-FET.
    Type: Application
    Filed: October 24, 2022
    Publication date: April 25, 2024
    Inventors: Chia-Kun Wu, Shao-Suz Ho, Wen-Yung Chang
  • Publication number: 20240128876
    Abstract: A switching control circuit for use in controlling a resonant flyback power converter generates a first driving signal and a second driving signal. The first driving signal is configured to turn on the first transistor to generate a first current to magnetize a transformer and charge a resonant capacitor. The transformer and charge a resonant capacitor are connected in series. The second driving signal is configured to turn on the second transistor to generate a second current to discharge the resonant capacitor. During a power-on period of the resonant flyback power converter, the second driving signal includes a plurality of short-pulses configured to turn on the second transistor for discharging the resonant capacitor. A pulse-width of the short-pulses of the second driving signal is short to an extent that the second current does not exceed a current limit threshold.
    Type: Application
    Filed: June 15, 2023
    Publication date: April 18, 2024
    Inventors: Yu-Chang Chen, Ta-Yung Yang, Kun-Yu Lin, Fu-Ciao Syu, Chia-Hsien Yang, Hsin-Yi Wu
  • Publication number: 20240120845
    Abstract: A resonant flyback power converter includes: a first transistor and a second transistor which are configured to switch a transformer and a resonant capacitor for generating an output voltage; and a switching control circuit generating first and second driving signals for controlling the first and the second transistors. The turn-on of the first driving signal magnetizes the transformer. The second driving signal includes a resonant pulse having a resonant pulse width and a ZVS pulse during the DCM operation. The resonant pulse is configured to demagnetize the transformer. The resonant pulse has a first minimum resonant period for a first level of the output load and a second minimum resonant period for a second level of the output load. The first level is higher than the second level and the second minimum resonant period is shorter than the first minimum resonant period.
    Type: Application
    Filed: April 14, 2023
    Publication date: April 11, 2024
    Inventors: Yu-Chang Chen, Ta-Yung Yang, Kun-Yu Lin, Hsin-Yi Wu
  • Publication number: 20240120846
    Abstract: A resonant flyback power converter includes: a first transistor and a second transistor which are configured to switch a transformer and a resonant capacitor for generating an output voltage; and a switching control circuit generating first and second driving signals for controlling the first and the second transistors. The turn-on of the first driving signal magnetizes the transformer. During a DCM (discontinuous conduction mode) operation, the second driving signal includes a resonant pulse for demagnetizing the transformer and a ZVS (zero voltage switching) pulse for achieving ZVS of the first transistor. The resonant pulse is skipped when the output voltage is lower than a low-voltage threshold.
    Type: Application
    Filed: April 14, 2023
    Publication date: April 11, 2024
    Inventors: Yu-Chang Chen, Ta-Yung Yang, Kun-Yu Lin, Hsin-Yi Wu
  • Publication number: 20240120844
    Abstract: A resonant flyback power converter includes: a first and a second transistors which form a half-bridge circuit for switching a transformer and a resonant capacitor to generate an output voltage; a current-sense device for sensing a switching current of the half-bridge circuit to generate a current-sense signal; and a switching control circuit generating a first and a second driving signals for controlling the first and the second transistors. The turn-on of the first driving signal controls the half-bridge circuit to generate a positive current to magnetize the transformer and charge the resonant capacitor. The turn-on of the second driving signal controls the half-bridge circuit to generate a negative current to discharge the resonant capacitor. The switching control circuit turns off the first transistor when the positive current exceeds a positive-over-current threshold, and/or, turns off the second transistor when the negative current exceeds a negative-over-current threshold.
    Type: Application
    Filed: April 10, 2023
    Publication date: April 11, 2024
    Inventors: Kun-Yu LIN, Ta-Yung YANG, Yu-Chang CHEN, Hsin-Yi WU, Fu-Ciao SYU, Chia-Hsien YANG
  • Publication number: 20240114414
    Abstract: Provided are a method and apparatus for providing a network switching service to a user equipment.
    Type: Application
    Filed: October 4, 2023
    Publication date: April 4, 2024
    Applicant: KT CORPORATION
    Inventors: Ji-Young JUNG, Kun-Woo PARK, Se-Hoon KIM, Il-Yong KIM, Sang-Hyun PARK, Ho-Jun JANG, Won-Chang CHO
  • Publication number: 20240106794
    Abstract: Provided are a method and apparatus for a user equipment, a core network, and a second device to enable bidirectional communication for second devices. The method of the second device may include receiving internet protocol (IP) configuration information for automatically configuring an IP version 6 (IPv6) address of the second device from a core network through a user equipment; generating the IPv6 address using information in the IP configuration information; and transmitting the generated IPv6 address to the core network through the UE.
    Type: Application
    Filed: September 6, 2023
    Publication date: March 28, 2024
    Applicant: KT CORPORATION
    Inventors: Won-Chang CHO, Se-Hoon KIM, Il-Yong KIM, Kun-Woo PARK, Sang-Hyun PARK, Ho-Jun JANG, Ji-Young JUNG
  • Publication number: 20240096776
    Abstract: A package substrate is provided and includes a core board body and a first circuit structure and a second circuit structure disposed on opposite sides of the core board body, where the number of wiring layers of the second circuit structure is different from the number of wiring layers of the first circuit structure, so that the package substrate is asymmetrical. The first circuit structure and the second circuit structure are designed according to the thickness and coefficient of thermal expansion of the first dielectric layer of the first circuit structure and the second dielectric layer of the second circuit structure, so as to prevent the problem of warping from occurring to the package substrate.
    Type: Application
    Filed: August 31, 2023
    Publication date: March 21, 2024
    Inventors: Andrew C. CHANG, Min-Yao CHEN, Sung-Kun LIN
  • Publication number: 20240098022
    Abstract: Provided are a method and apparatus for providing a multi virtual local area network service to user equipments.
    Type: Application
    Filed: September 19, 2023
    Publication date: March 21, 2024
    Applicant: KT CORPORATION
    Inventors: Ho-Jun JANG, Se-Hoon KIM, Won-Chang CHO, Sang-Hyun PARK, Kun-Woo PARK, Ji-Young JUNG
  • Patent number: 11935935
    Abstract: A thin film transistor includes a gate electrode embedded in an insulating layer that overlies a substrate, a gate dielectric overlying the gate electrode, an active layer comprising a compound semiconductor material and overlying the gate dielectric, and a source electrode and drain electrode contacting end portions of the active layer. The gate dielectric may have thicker portions over interfaces with the insulating layer to suppress hydrogen diffusion therethrough. Additionally or alternatively, a passivation capping dielectric including a dielectric metal oxide material may be interposed between the active layer and a dielectric layer overlying the active layer to suppress hydrogen diffusion therethrough.
    Type: Grant
    Filed: November 11, 2021
    Date of Patent: March 19, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Min-Kun Dai, Wei-Gang Chiu, I-Cheng Chang, Cheng-Yi Wu, Han-Ting Tsai, Tsann Lin, Chung-Te Lin
  • Publication number: 20240088266
    Abstract: A fin structure on a substrate is disclosed. The fin structure can comprises a first epitaxial region and a second epitaxial region separated by a dielectric region, a merged epitaxial region on the first epitaxial region and the second epitaxial region, an epitaxial buffer region on a top surface of the merged epitaxial region, and an epitaxial capping region on the buffer epitaxial region and side surfaces of the merged epitaxial region.
    Type: Application
    Filed: November 16, 2023
    Publication date: March 14, 2024
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsueh-Chang SUNG, Kun-Mu LI
  • Publication number: 20240087105
    Abstract: A method for detecting paint defects on objects is provided. The method comprises: projecting a plurality of patterns on a surface of an object at a plurality of different pattern characteristics; capturing a plurality of images of the object based on projecting the plurality of patterns; inputting the plurality of images of the object into a machine learning model to determine whether the surface of the object includes one or more paint defects; and based on determining, an image, of the plurality of images, includes a paint defect, causing display of the image with the paint defect.
    Type: Application
    Filed: January 26, 2021
    Publication date: March 14, 2024
    Applicant: ABB Schweiz AG
    Inventors: Nevroz Sen, WenLong Li, Amber-FengQin Zhu, Kun Chang
  • Publication number: 20240071523
    Abstract: A memory device and a programming method thereof are provided. The programming method includes the following steps. According to a step value, based on an incremental step pulse programming scheme, multiple programming operations are performed for a selected memory page. In a setting mode, multiple program verify operations are respectively performed corresponding to the programming operations to respectively generate multiple pass bit numbers. In the setting mode, a pass bit number difference value of two pass bit numbers corresponding to two programming operations is calculated. In the setting mode, an amount of the step value is adjusted according to the pass bit number difference value.
    Type: Application
    Filed: August 24, 2022
    Publication date: February 29, 2024
    Applicant: MACRONIX International Co., Ltd.
    Inventors: Kun-Tse Lee, Han-Sung Chen, Shih-Chang Huang
  • Publication number: 20240070933
    Abstract: A method for correcting location of a virtual target in a patient during a live procedure comprises segmenting the organ and the real target from an initial pre-procedure image data set; receiving a live procedure image data set of the patient including the organ and the real target and camera tracking information; registering the initial pre-procedure image data set and the live image data set; determining a candidate location of a virtual target for the real target based on the initial registration; generating a first image at a first view angle showing the virtual target and the real target; adjusting the candidate location of the virtual target to match the actual location of the real target in the first image; and computing a corrected location for the virtual target based on the adjusting step. Related systems are disclosed.
    Type: Application
    Filed: August 16, 2023
    Publication date: February 29, 2024
    Inventors: Ernest Woei, Kun-Chang Yu, Matthew Mctaggart, Abbe Smith
  • Publication number: 20240060776
    Abstract: The present disclosure relates to a laser level system. The laser level system includes a mount, a laser secured to the mount and a remove input device. The mount includes a rotating portion to which the laser level is secured. The remote input device controls rotation of the rotating portion. The laser level is secured to the rotating portion of the mount such that when the rotating portion rotates, the laser level rotates concurrently along with the rotating portion of the mount.
    Type: Application
    Filed: October 24, 2023
    Publication date: February 22, 2024
    Applicant: Stanley Black & Decker Inc.
    Inventors: Bruce EIDINGER, Kun CHANG
  • Patent number: 11896312
    Abstract: A lung tumor ablation planning system includes a processor operable to compute a target ablation zone and a set of optimum ablation parameters to create the target lesion with the ablation catheter. A predictive algorithm is employed to model the ablation zone based on training data. Various ablation plans are displayed to the physician corresponding to various metrics including without limitation maximizing tumor ablation coverage, shortest travel, obstacle avoidance, and shortest ablation time. Related methods are described.
    Type: Grant
    Filed: February 4, 2019
    Date of Patent: February 13, 2024
    Assignee: BRONCUS MEDICAL INC.
    Inventors: Yixun Liu, Ronnarit Cheirsilp, Kun-Chang Yu, Henky Wibowo
  • Patent number: 11863803
    Abstract: The present disclosure relates to the field of network live streaming, and provides a live streaming interface interaction method and apparatus, an electronic device, and a computer-readable medium. The method comprises: displaying, on a live streaming interface, a first function control and a second function control used for indicating the same function state; receiving an interactive operation acting on the live streaming interface, and switching the function state of the first function control and the second function control when it is determined that the interactive operation meets a preset condition; and respectively displaying corresponding guide animations on display positions corresponding to the first function control and the second function control, so as to prompt a user to perform the next interactive operation.
    Type: Grant
    Filed: December 29, 2022
    Date of Patent: January 2, 2024
    Inventors: Wenjing Liu, Cheng Chi, Kun Chang, Guizhang Chen, Yu Li, Chenkang Li, Meng Chen, Zhenwei Lai, Yingke Wang
  • Patent number: D1025183
    Type: Grant
    Filed: December 29, 2022
    Date of Patent: April 30, 2024
    Assignee: ViewSonic International Corporation
    Inventors: Jia-Shin Tsai, Shun-Chang Chen, Kun-Tsang Yang