Abstract: An optical element driving mechanism is provided and includes a fixed assembly, a movable assembly, a driving assembly and a stopping assembly. The fixed assembly has a main axis. The movable assembly is configured to connect an optical element, and the movable assembly is movable relative to the fixed assembly. The driving assembly is configured to drive the movable assembly to move relative to the fixed assembly. The stopping assembly is configured to limit the movement of the movable assembly relative to the fixed assembly within a range of motion.

Abstract: In a decoder of a digital-to-analog converter, the gamma voltage selection is controlled by a reduced number of NMOS and PMOS transistors according to the characteristic of the NMOS and PMOS transistor, such that the layout area of the switch array is reduced. Moreover, a N-type buried diffusion (BDN) layer and a P-type buried diffusion (BDP) layer are adopted to replace the contacts in the layout of conventional decoder, such that the layout can be simplified and the bump pad pitch thereof can be decreased.

Abstract: A capacitor digital-to-analog converter for N-bit digital-to-analog conversion comprises a converter capacitor network comprising 2N capacitors and 2N+1 MOS switches and an output buffer. The MOS switches are connected in a series chain at their respective source/drain, and each of the capacitors has a first electrode connected to a corresponding joining node between two consecutive MOS switches in the series chain and a second electrode connected together to a common node. The output buffer comprises a differential amplifier and an output amplifier, the differential amplifier has 2N discrete inputs each connected to a corresponding one of the first electrodes of the capacitors in the converter capacitor network.

Abstract: A decoder of a digital-to-analog converter is disclosed. In the present invention, the gamma voltage selection is controlled by a reduced number of NMOS and PMOS transistors according to the characteristic of the NMOS and PMOS transistor, such that the layout area of the switch array is reduced. Moreover, a N-type buried diffusion (BDN) layer and a P-type buried diffusion (BDP) layer are adopted to replace the contacts in the layout of conventional decoder, such that the layout can be simplified and the bump pad pitch thereof can be decreased.

Abstract: A circuit for predicting the dead time is provided. The circuit comprises a plurality of integrators, a plurality of comparators, and a logic circuit. Based on a reference signal provided externally, a first charging operation is delayed by a predetermined delay time during one period of the reference signal, such that the integrators maintain at a voltage level in a next period of the reference signal. Then, the integrators further perform another charging operation during the next period, and the charging voltage is compared with the maintained voltage value. When the charging voltage exceeds the maintained voltage, a reset signal is generated by the logic circuit.

Abstract: A circuit for predicting the dead time is provided. The circuit includes a plurality of integrators, a plurality of comparators, and a logic circuit. Based on a reference signal provided externally, a first charging operation is delayed by a predetermined delay time during one period of the reference signal, such that the integrators maintain at a voltage level in a next period of the reference signal. Then, the integrators further perform another charging operation during the next period, and the charging voltage is compared with the maintained voltage value. When the charging voltage exceeds the maintained voltage, a reset signal is generated by the logic circuit.

Abstract: An apparatus for recycling energy in a liquid crystal display (LCD) so as to reduce energy loss when the LCD is driven by a driving circuit. The LCD includes two pixels, each of which has a corresponding capacitor and has a corresponding voltage applied to. The polarities of the voltages of the two corresponding capacitors are variable with time and are opposite to each other. The apparatus includes two switches and an energy converter. The two switches are used for selectively coupling the respective capacitors to the apparatus. The energy converter is used for outputting converted energy according to the voltages of the two capacitors. By enabling the first switch and the second switch selectively, the apparatus recycles energy dissipated during polarity inversion for the two pixels as energy for driving a load device.

Abstract: An apparatus for switching output voltage signals includes a resistor string, a first switching device set for delivering a number of gamma voltage input signals, a second switching device set for delivering a high voltage input signal and a low voltage input signal, and a switch selecting device coupled to the first switching device set and the second switching device set. When the switch selecting device outputs a first signal, the first switching device set can deliver the gamma voltage input signals to the resistor string; when the switch selecting device outputs a second signal, the second switching device set will deliver the high voltage input signal and the low voltage input signal to the resistor string.

Abstract: A dynamic CMOS level shifter circuit apparatus in a digital electronic system is disclosed for shifting a signal of a first logic family at a first lower voltage level to a second higher voltage level for a second logic family. The shifter circuit apparatus comprises a first transistor pair that has a first PMOS and a first NMOS transistor connected in series; a second transistor pair that has a second PMOS and a second NMOS transistor connected in series; and a power-down control PMOS transistor. The first and second transistor pairs are connected in parallel, and the parallel connection is connected in series with the power-down control PMOS transistor across the power and ground level of the system. The node at which the drain terminals of the transistors of the first transistor pair is connected together is also connected to the gate of the second PMOS transistor.

Abstract: A testing method and a testing a voltages apparatus embedded in the scribe line on a wafer are disclosed, for testing the to be measured from a die on a wafer. The testing apparatus includes a multiplexer and a comparator. The multiplexer receives the voltages to be measured and outputs a multiplexing or selected voltage according to a selection signal. The comparator receives a reference voltage and the multiplexing voltage and then outputs a digital result by comparing the reference voltage, and the multiplexing voltage. The digital result can be applied to a digital testing machine, such that testing speed is increased and testing cost is decreased. Moreover, the testing apparatus embedded in the scribe lines has the capability to compensate for the comparator's offset, and accordingly, the testing reliability is also improved.

Abstract: A layout structure of a decoder with m*n nodes and the method thereof are provided. The nodes comprise a plurality of transistor nodes and a plurality of channel nodes. The manufacturing method of the transistor node comprises forming a gate, a first source/drain region and a second source/drain region. The channel node is fabricated by forming a channel. The channel, the first source/drain region and the second source/drain region are formed at the same time with the same material. The decoder circuit with smaller width is accomplished without additional mask in the invention.

Abstract: An apparatus for recycling energy in a liquid crystal display (LCD) so as to reduce energy loss when the LCD is driven by a driving circuit. The LCD includes two pixels, each of which has a corresponding capacitor and has a corresponding voltage applied to. The polarities of the voltages of the two corresponding capacitors are variable with time and are opposite to each other. The apparatus includes two switches and an energy converter. The two switches are used for selectively coupling the respective capacitors to the apparatus. The energy converter is used for outputting converted energy according to the voltages of the two capacitors. By enabling the first switch and the second switch selectively, the apparatus recycles energy dissipated during polarity inversion for the two pixels as energy for driving a load device.

Abstract: An apparatus for switching output voltage signals includes a resistor string, a first switching device set for delivering a number of gamma voltage input signals, a second switching device set for delivering a high voltage input signal and a low voltage input signal, and a switch selecting device coupled to the first switching device set and the second switching device set. When the switch selecting device outputs a first signal, the first switching device set can deliver the gamma voltage input signals to the resistor string; when the switch selecting device outputs a second signal, the second switching device set will deliver the high voltage input signal and the low voltage input signal to the resistor string.

Abstract: A testing method and a testing apparatus embedded in the scribe line on the wafer are disclosed, for testing the voltages to be measured from a die on a wafer. The testing apparatus comprises a multiplexer and a comparator. The multiplexer receives the voltages to be measured and outputs a multiplexing voltage according to a selection signal. The comparator receives a reference voltage and the multiplexing voltage and then outputs a digital result by comparing the reference voltage, and the multiplexing voltage. The digital result can be applied to a digital testing machine, such that testing speed is increased and testing cost is decreased. Moreover, the testing apparatus embedded in the scribe lines has the capability to compensate the comparator's offset, and accordingly, the testing reliability is also improved.

Abstract: A capacitor digital-to-analog converter for N-bit digital-to-analog conversion comprises a converter capacitor network comprising 2N capacitors and 2N+1 MOS switches and an output buffer. The MOS switches are connected in a series chain at their respective source/drain, and each of the capacitors has a first electrode connected to a corresponding joining node between two consecutive MOS switches in the series chain and a second electrode connected together to a common node. The output buffer comprises a differential amplifier and an output amplifier, the differential amplifier has 2N discrete inputs each connected to a corresponding one of the first electrodes of the capacitors in the converter capacitor network.

Abstract: A layout structure of a decoder with m*n nodes and the method thereof are provided. The nodes comprise a plurality of transistor nodes and a plurality of channel nodes. The manufacturing method of the transistor node comprises forming a gate, a first source/drain region and a second source/drain region. The channel node is fabricated by forming a channel. The channel, the first source/drain region and the second source/drain region are formed at the same time with the same material. The decoder circuit with smaller width is accomplished without additional mask in the invention.