Abstract: A transparent display panel with driving electrode regions, circuit wiring regions, and optically transparent regions is provided. The driving electrode regions are arranged into an array in a first direction and a second direction. An average light transmittance of the circuit wiring regions is less than ten percent, and an average light transmittance of the optically transparent regions is greater than that of the driving electrode regions and the circuit wiring regions. The first direction intersects the second direction. The circuit wiring regions connect the driving electrode regions at intervals, such that each optically transparent region spans among part of the driving electrode regions. The transparent display panel includes first signal lines and second signal lines extending along the circuit wiring regions, and each circuit wiring region is provided with at least one of the first signal lines and at least one of the second signal lines.

Abstract: A power-saving luminous basketball hoop set has a base, an illuminating module, and a basketball hoop assembly. The base has a cavity. The illuminating module is mounted in the cavity and has a control circuit module and an LED module electrically connected to each other. The control circuit module has a vibration sensor and an MCU. The basketball hoop assembly is fixed in the base and has a light-transmitting backboard and a rim assembly fixed on the light-transmitting backboard. The light-transmitting backboard is inserted in the cavity and is adjacent to the LED module. The power-saving luminous basketball hoop set can be automatically lighted up by detecting vibration.

Abstract: A basketball shooting training includes a stand, a rotatable hoop module, a blocking module, and a guide module. The stand includes a horizontal segment and a vertical segment. The rotatable hoop module includes a frame and a backboard. The blocking module includes two columns, a collection member, an obstruction unit, and two fixed pulley sets. The guide module includes a conducting device mounted on the horizontal segment of the stand, and the supply portion extends outward from the stand. The mounting of the stand is fixed on a bottom of the conducting device, and the rotatable hoop module further includes a support post on which the backboard is disposed. A movable seat is connected on a bottom of the support post, the movable seat is disposed on and rotates along the mounting, and the conducting device has an arcuate track on which the support post slides.

Abstract: A fast methodology and system to characterize setup/hold time for analog IPs are provided. Partial circuits of clock and data paths are simulated instead of the simulation of entire IPs. The partial circuits include all those paths of clock pin and data input pins before reaching first level DFF. This methodology includes multi-path searching of hierarchical SPICE netlist for the path of clock pin and data pins, so as to reduce the circuit subset, merge the paths of clock pin and the data pins, and characterize the setup/hold time for the analog IP. The paths of data pins and clock pin before DFF are used for setup/hold time characterization.

Abstract: A fast methodology and system to characterize setup/hold time for analog IPs are provided. Partial circuits of clock and data paths are simulated instead of the simulation of entire IPs. The partial circuits include all those paths of clock pin and data input pins before reaching first level DFF. This methodology includes multi-path searching of hierarchical SPICE netlist for the path of clock pin and data pins, so as to reduce the circuit subset, merge the paths of clock pin and the data pins, and characterize the setup/hold time for the analog IP. The paths of data pins and clock pin before DFF are used for setup/hold time characterization.

Abstract: A method for reducing standard delay format (SDF) file size is disclosed. The state-dependent descriptions in cell descriptions of the SDF file, which are not intended to be used, are removed by referring to a design description of an integrated circuit design. Therefore, the SDF file size is reduced and the simulation result generated by a simulator is not affected with the reduced SDF file.

Abstract: A method for static power characterization of an analog integrated circuit includes detecting whether each of a plurality of input pins is electrically connected to a specific circuit; selecting a plurality of test benches of the static power characterization according to a number of the input pins electrically connected to the specific circuit; and processing the plurality of selected test benches of the static power characterization.

Abstract: A method of generating a protected standard delay format (SDF) file is disclosed. The interconnect delay descriptions of a SDF file are backwardly or forwardly integrated into the related cell delay descriptions according to their interconnection type to generate the protected SDF file. The total delay value of each signal path is the same as original, so that the simulation result generated by a simulator is not affected.

Abstract: A method of generating a protected standard delay format (SDF) file is disclosed. The interconnect delay descriptions of a SDF file are backwardly or forwardly integrated into the related cell delay descriptions according to their interconnection type to generate the protected SDF file. The total delay value of each signal path is the same as original, so that the simulation result generated by a simulator is not affected.

Abstract: A method for reducing standard delay format (SDF) file size is disclosed. The state-dependent descriptions in cell descriptions of the SDF file, which are impossible to be used, are removed by referring to a design description of an integrated circuit design. Therefore, the SDF file size is reduced and the simulation result generated by a simulator is not affected with the reduced SDF file.

Abstract: A method for preventing redundant events from toggling the core logic during scan data shifting mode is provided. A logic element is controlled by SEL. During scan data shifting mode, no toggled data will interfere with the core logic because the logic element is shut off. Only the scan path (SI-SO-SI) continues toggling. Therefore, redundant events are prevented from toggling the core logic. Therefore the simulation time is reduced and the verification flow is sped up. Additionally, the power consumption during testing is significantly reduced.

Abstract: A processor is provided with a decoder, a memory connected to the decoder and an execution stage connected to the decoder. The decoder receives each instruction. Each time the decoder receives an instruction, if the instruction contains a symbolic reference, the decoder determines whether or not the symbolic reference has been resolved into a numeric operand. If the symbolic reference has been resolved into a numeric operand, the memory retrieves, from a numeric reference table, a numeric operand to which the symbolic reference has been resolved. The execution stage then executes the instruction on the retrieved numeric operand in place of the symbolic reference. If the symbolic reference has not been resolved into a numeric operand, then the execution stage searches a data object, which relates each symbolic reference to a memory slot in which a corresponding numeric operand is stored, for a numeric reference relating the symbolic reference to a corresponding numeric operand.

Abstract: A river is divided into a plurality of river sections via a plurality of partitions which are spaced apart along the direction of the flow of the river. Polluted water at or near the surface of the river from the river sections is pumped to water treating apparatuses without drawing the polluted water near the floor of the river. Suspension pollutants, including nitrogenous nutrients, are removed from the polluted water via filtration in the water treating apparatuses. After treatment, the treated water is sent to the river in such a manner that the water drawn from each river section is sent to another one of the river sections, that is located immediately downstream, at the same rate as the river flow and that the remaining portion of the treated water is sent back to the upstream river section from where the water comes.

Abstract: A refuse incinerating oven includes a refuse loading car, and a furnace body with lower and upper combustion chambers. The car is conveyed through the furnace body such that refuse loaded on the car can be ignited in the lower combustion chamber. The combustion exhaust generated in the lower combustion chamber flows into and is heated in the upper combustion chamber. A spraying tank is communicated with the upper combustion chamber for receiving the combustion exhaust. Water mist is sprayed to the combustion exhaust in the spraying tank so as to generate aerated water. The aerated water and the combustion exhaust flowing from the spraying tank are cooled as they flow into a reservoir. The aerated water is pumped from the reservoir to an upper end of a waterfall tank so as to generate a downwardly cascading water stream inside the waterfall tank. An exhaust port unit is connected to the upper end of the waterfall tank for sucking and releasing the combustion exhaust.

Abstract: A processor architecture is disclosed including a fetcher, packet unit and branch target buffer. The branch target buffer is provided with a tag RAM that is organized in a set associative fashion. In response to receiving a search address, multiple sets in the tag RAM are simultaneously searched for a branch instruction that is predicted to be taken. The packet unit has a queue into which fetched cache blocks are stored containing instructions. Sequentially fetched cache blocks are stored in adjacent locations of the queue. The queue entries also have indicators that indicate whether or not a starting or final data word of an instruction sequence is contained in the queue entry and if so, an offset indicating the particular starting or final data word. In response, the packet unit concatenates data words of an instruction sequence into contiguous blocks. The fetcher generates a fetch address for fetching a cache block from the instruction cache containing instructions to be executed.

Abstract: A processor architecture is disclosed including a fetcher, packet unit and branch target buffer. The branch target buffer is provided with a tag RAM that is organized in a set associative fashion. In response to receiving a search address, multiple sets in the tag RAM are simultaneously searched for a branch instruction that is predicted to be taken. The packet unit has a queue into which fetched cache blocks are stored containing instructions. Sequentially fetched cache blocks are stored in adjacent locations of the queue. The queue entries also have indicators that indicate whether or not a starting or final data word of an instruction sequence is contained in the queue entry and if so, an offset indicating the particular starting or final data word. In response, the packet unit concatenates data words of an instruction sequence into contiguous blocks. The fetcher generates a fetch address for fetching a cache block from the instruction cache containing instructions to be executed.

Abstract: An improved method and apparatus for buffering and issuing instructions for use with superscalar microprocessors are disclosed.