Abstract: The present disclosure describes a method that mitigates the formation of facets in source/drain silicon germanium (SiGe) epitaxial layers. The method includes forming an isolation region around a semiconductor layer and a gate structure partially over the semiconductor layer and the isolation region. Disposing first photoresist structures over the gate structure, a portion of the isolation region, and a portion of the semiconductor layer and doping, with germanium (Ge), exposed portions of the semiconductor layer and exposed portions of the isolation region to form Ge-doped regions that extend from the semiconductor layer to the isolation region. The method further includes disposing second photoresist structures over the isolation region and etching exposed Ge-doped regions in the semiconductor layer to form openings, where the openings include at least one common sidewall with the Ge-doped regions in the isolation region. Finally the method includes growing a SiGe epitaxial stack in the openings.

Abstract: A semiconductor device and method of manufacturing the same are provided. The semiconductor device includes a substrate and a gate structure disposed on the substrate. The semiconductor device also includes a source region and a drain region disposed within the substrate. The substrate includes a drift region laterally extending between the source region and the drain region. The semiconductor device further includes a first stressor layer disposed over the drift region of the substrate. The first stressor layer is configured to apply a first stress to the drift region of the substrate. In addition, the semiconductor device includes a second stressor layer disposed on the first stressor layer. The second stressor layer is configured to apply a second stress to the drift region of the substrate, and the first stress is opposite to the second stress.

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, a stacked gate structure, and a wall structure. The stacked gate structure is on the substrate and extending along a first direction. The wall structure is on the substrate and laterally aside the stacked gate structure. The wall structure extends along the first direction and a second direction perpendicular to the first direction. The stacked gate structure is overlapped with the wall structure in the first direction and the second direction.

Abstract: A method of manufacturing a printed circuit board with embedded electronic components fixed by a solder paste includes: providing a carrier board with a copper foil layer on the carrier board, an insulating layer on the copper foil layer, and an opening on the insulating layer by laser; putting a solder paste into the opening to form a solder paste layer; performing a high-temperature reflow process of the electronic components on the solder paste layer until the solder paste layer is molten; curing the solder paste layer after cooling to fix the components to the center position of the opening; placing the copper foil layer below the electronic components and removing the solder paste layer; and performing copper plating and electroplating processes in an electroplating space to form a plating copper. The cohesion of the molten solder paste pulls the electronic components towards the center to eliminate position offset produced when the electronic components are installed.

Abstract: A method of manufacturing a printed circuit board with embedded electronic components fixed by a solder paste includes: providing a carrier board with a copper foil layer on the carrier board, an insulating layer on the copper foil layer, and an opening on the insulating layer by laser; putting a solder paste into the opening to form a solder paste layer; performing a high-temperature reflow process of the electronic components on the solder paste layer until the solder paste layer is molten; curing the solder paste layer after cooling to fix the components to the center position of the opening; placing the copper foil layer below the electronic components and removing the solder paste layer; and performing copper plating and electroplating processes in an electroplating space to form a plating copper. The cohesion of the molten solder paste pulls the electronic components towards the center to eliminate position offset produced when the electronic components are installed.

Abstract: A method for directly attaching dielectric to a circuit board with embedded electronic devices is provided. That is, a plurality of through holes are produced before embedding an electronic device, wherein plural through holes are corresponding to a plurality of electrodes of the electronic device. So that the plural electrodes of the electronic device is accurately positioned with the through holes if the electronic device is being embedded. On the other hand, since the first dielectric layer is adhesive, the electronic device is directly stuck on the first dielectric layer in order to save cost of adhesive material or metal conductive paste in prior arts.

Abstract: A nail gun includes a nail gun housing, a nail magazine detachably mounted in the nail gun housing and defining with the nail gun housing a nail crown receiving space and first, second and third nail leg receiving spaces, and a nail pusher for pushing a nail to a nailing position in the nail magazine, the nail pusher having a top portion positioned in the nail crown receiving space and first, second and third push portions respectively downwardly extended from two lateral sides and a second side of the top portion and respectively inserted into the first, second and third nail leg receiving spaces. Thus, a large contact surface area of the nail pusher can be abutted against the leg(s) of one of various types of nails to keep the nail accurately in the nailing position, avoiding tilting or any nailing errors.

Abstract: A method of manufacturing a multilayer printed circuit board of a built-in electronic device provides a substrate having a copper clad laminate and a first dielectric layer. The first dielectric layer is laminated onto the copper clad laminate and has a cavity for accommodating the electronic device. A second dielectric layer is laminated onto the substrate and electronic device to produce a base circuit board with an embedded electronic device. A build-up circuit layer is formed on the base circuit board. The first and second dielectric layers are made of a plastic material.

Abstract: A method of manufacturing a multilayer printed circuit board of a built-in electronic device provides a substrate having a copper clad laminate and a first dielectric layer. The first dielectric layer is laminated onto the copper clad laminate and has a cavity for accommodating the electronic device. A second dielectric layer is laminated onto the substrate and electronic device to produce a base circuit board with an embedded electronic device. A build-up circuit layer is formed on the base circuit board. The first and second dielectric layers are made of a plastic material.