Patents by Inventor Kun-Chi Chen

Kun-Chi Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200343289
    Abstract: An image sensor device is provided. The image sensor device includes a semiconductor substrate having a first side, a second side opposite to the first side, and at least one light-sensing region close to the first side. The image sensor device includes a dielectric feature covering the second side and extending into the semiconductor substrate. The dielectric feature in the semiconductor substrate surrounds the light-sensing region. The image sensor device includes a reflective layer in the dielectric feature in the semiconductor substrate, wherein a top portion of the reflective layer protrudes away from the second side, and a top surface of the reflective layer and a top surface of the insulating layer are substantially coplanar.
    Type: Application
    Filed: July 9, 2020
    Publication date: October 29, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Chieh FANG, Ming-Chi WU, Ji-Heng JIANG, Chi-Yuan WEN, Chien-Nan TU, Yu-Lung YEH, Shih-Shiung CHEN, Kun-Yu LIN
  • Patent number: 10790391
    Abstract: The present disclosure describes a method that mitigates the formation of facets in source/drain silicon germanium (SiGe) epitaxial layers. The method includes forming an isolation region around a semiconductor layer and a gate structure partially over the semiconductor layer and the isolation region. Disposing first photoresist structures over the gate structure, a portion of the isolation region, and a portion of the semiconductor layer and doping, with germanium (Ge), exposed portions of the semiconductor layer and exposed portions of the isolation region to form Ge-doped regions that extend from the semiconductor layer to the isolation region. The method further includes disposing second photoresist structures over the isolation region and etching exposed Ge-doped regions in the semiconductor layer to form openings, where the openings include at least one common sidewall with the Ge-doped regions in the isolation region. Finally the method includes growing a SiGe epitaxial stack in the openings.
    Type: Grant
    Filed: August 30, 2018
    Date of Patent: September 29, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Gulbagh Singh, Hsin-Chi Chen, Kun-Tsang Chuang
  • Publication number: 20200295046
    Abstract: Bulk semiconductor substrates configured to exhibit semiconductor-on-insulator (SOI) behavior, and corresponding methods of fabrication, are disclosed herein. An exemplary bulk substrate configured to exhibit SOI behavior includes a first isolation trench that defines a channel region of the bulk substrate and a second isolation trench that defines an active region that includes the channel region. The first isolation trench includes a first isolation trench portion and a second isolation trench portion disposed over the first isolation trench portion. A first isolation material fills the first isolation trench portion, and an epitaxial material fills the second isolation trench portion. The epitaxial material is disposed on the first isolation material. A second isolation material fills the second isolation trench. A portion of the bulk substrate underlying the first isolation trench and the channel region is configured to have a higher resistance than the bulk substrate.
    Type: Application
    Filed: June 1, 2020
    Publication date: September 17, 2020
    Inventors: Gulbagh Singh, Kun-Tsang Chuang, Hsin-Chi Chen
  • Publication number: 20200247101
    Abstract: A method for preparing a bifunctional film, including: (a) drying a first polymer solution to form a film to form an anti-adhesion layer; and (b) drying a second polymer solution over the anti-adhesion layer to form a film to form an attachment layer. The first polymer solution includes a first hydrophobic solution and a first hydrophilic solution, and in the first polymer solution, the weight ratio of the solute of the first hydrophobic solution to the solute of the first hydrophilic solution 1:0.01-1. Moreover, the second polymer solution consists of a second hydrophilic solution.
    Type: Application
    Filed: November 6, 2019
    Publication date: August 6, 2020
    Applicant: Industrial Technology Research Institute
    Inventors: Hsin-Hsin SHEN, Yu-Chi WANG, Ming-Chia YANG, Yu-Bing LIOU, Wei-Hong CHANG, Yun-Han LIN, Hsin-Yi HSU, Yun-Chung TENG, Chia-Jung LU, Yi-Hsuan LEE, Jian-Wei LIN, Kun-Mao KUO, Ching-Mei CHEN
  • Publication number: 20200251554
    Abstract: The present disclosure describes a fabrication method that prevents divots during the formation of isolation regions in integrated circuit fabrication. In some embodiments, the method of forming the isolation regions includes depositing a protective layer over a semiconductor layer; patterning the protective layer to expose areas of the semiconductor layer; depositing an oxide on the exposed areas the semiconductor layer and between portions of the patterned protective layer; etching a portion of the patterned protective layer to expose the semiconductor layer; etching the exposed semiconductor layer to form isolation openings in the semiconductor layer; and filling the isolation openings with a dielectric to form the isolation regions.
    Type: Application
    Filed: April 22, 2020
    Publication date: August 6, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Gulbagh SINGH, Hsin-Chi CHEN, Kun-Tsang CHUANG
  • Patent number: 10734427
    Abstract: A method for forming an image sensor device is provided. The method includes providing a semiconductor substrate including a front surface, a back surface opposite to the front surface, at least one light-sensing region close to the front surface, and a first trench surrounding the light-sensing region. The method includes forming an insulating layer over the back surface and in the first trench. A void is formed in the insulating layer in the first trench, and the void is closed. The method includes removing the insulating layer over the void to open up the void. The opened void forms a second trench partially in the first trench. The method includes filling a reflective structure in the second trench. The reflective structure has a light reflectivity ranging from about 70% to about 100%.
    Type: Grant
    Filed: February 15, 2019
    Date of Patent: August 4, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Chieh Fang, Ming-Chi Wu, Ji-Heng Jiang, Chi-Yuan Wen, Chien-Nan Tu, Yu-Lung Yeh, Shih-Shiung Chen, Kun-Yu Lin
  • Patent number: 10672795
    Abstract: Bulk semiconductor substrates configured to exhibit semiconductor-on-insulator (SOI) behavior, and corresponding methods of fabrication, are disclosed herein. An exemplary bulk substrate configured to exhibit SOI behavior includes a first isolation trench that defines a channel region of the bulk substrate and a second isolation trench that defines an active region that includes the channel region. The first isolation trench includes a first isolation trench portion and a second isolation trench portion disposed over the first isolation trench portion. A first isolation material fills the first isolation trench portion, and an epitaxial material fills the second isolation trench portion. The epitaxial material is disposed on the first isolation material. A second isolation material fills the second isolation trench. A portion of the bulk substrate underlying the first isolation trench and the channel region is configured to have a higher resistance than the bulk substrate.
    Type: Grant
    Filed: August 30, 2018
    Date of Patent: June 2, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Gulbagh Singh, Kun-Tsang Chuang, Hsin-Chi Chen
  • Publication number: 20200152648
    Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, a stacked gate structure, and a wall structure. The stacked gate structure is on the substrate and extending along a first direction. The wall structure is on the substrate and laterally aside the stacked gate structure. The wall structure extends along the first direction and a second direction perpendicular to the first direction. The stacked gate structure is overlapped with the wall structure in the first direction and the second direction.
    Type: Application
    Filed: January 13, 2020
    Publication date: May 14, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chien-Hsuan Liu, Chiang-Ming Chuang, Chih-Ming Lee, Kun-Tsang Chuang, Hung-Che Liao, Chia-Ming Pan, Hsin-Chi Chen
  • Patent number: 10636870
    Abstract: The present disclosure describes a fabrication method that prevents divots during the formation of isolation regions in integrated circuit fabrication. In some embodiments, the method of forming the isolation regions includes depositing a protective layer over a semiconductor layer; patterning the protective layer to expose areas of the semiconductor layer; depositing an oxide on the exposed areas the semiconductor layer and between portions of the patterned protective layer; etching a portion of the patterned protective layer to expose the semiconductor layer; etching the exposed semiconductor layer to form isolation openings in the semiconductor layer; and filling the isolation openings with a dielectric to form the isolation regions.
    Type: Grant
    Filed: August 15, 2018
    Date of Patent: April 28, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Gulbagh Singh, Hsin-Chi Chen, Kun-Tsang Chuang
  • Patent number: 10630185
    Abstract: A power delivery device and a control method are shown. The power delivery device includes a power factor correction circuit, and an output voltage control circuit. The power factor correction circuit is configured to increase a power factor of the power delivery device. The output voltage control circuit is configured to control an output voltage of the power delivery device, and detect an output current of the power delivery device. The power factor correction circuit is uncontrolled by the output voltage control circuit in response to a first load state of the power delivery device, and is controlled by the output voltage control circuit in response to a second load state of the power delivery device.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: April 21, 2020
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Kun-Chi Lin, Chung-Chieh Cheng, Kun-Jang Kuo, Tien-He Chen, Shou-Chieh Lin
  • Publication number: 20200089894
    Abstract: A data-processing device is provided. The data-processing device includes: a flash memory, a computation unit, and a flash-memory controller. The flash-memory controller is electrically connected to the computation unit, and configured to control access to the flash memory. The flash-memory controller allocates a first execute-only memory (XOM) setting and a second XOM setting in a first memory bank and a second memory bank of the flash memory, respectively. The flash-memory controller allocates one or more XOM spaces in the flash memory according to the first XOM setting or the second XOM setting.
    Type: Application
    Filed: May 30, 2019
    Publication date: March 19, 2020
    Inventors: Ming-Ying LIU, Kun-Yi WU, Chun-Chi CHEN
  • Patent number: 10591646
    Abstract: An infrared anti-reflection film structure, an anti-reflection film layer, including a material of zinc oxide, comprising a top anti-reflection film layer and a bottom anti-reflection film layer, wherein the top anti-reflection film layer is disposed on a top side of the base material and the bottom anti-reflection film layer is disposed on a bottom side of the base material; and the base material is manufactured by a floating zone crystal growth method. Through the silicon base material manufactured by the high purity crystal growth method, the silicon base material replaces germanium as the high refractive index material and base material. And coating the anti-reflection film layer on the surface of the silicon base material, so as to apply the infrared anti-reflection film structure to the thermal imaging technology.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: March 17, 2020
    Assignee: National Chung-Shan Institute of Science and Technology
    Inventors: Shih-Hao Chan, Shiang-Feng Tang, Shao-Ze Tseng, Kun-Chi Lo, Sheng-Hui Chen, Wen-Jen Lin
  • Publication number: 20200083389
    Abstract: An image sensor with an absorption enhancement semiconductor layer is provided. In some embodiments, the image sensor comprises a front-side semiconductor layer, an absorption enhancement semiconductor layer, and a back-side semiconductor layer that are stacked. The absorption enhancement semiconductor layer is stacked between the front-side and back-side semiconductor layers. The absorption enhancement semiconductor layer has an energy bandgap less than that of the front-side semiconductor layer. Further, the image sensor comprises a plurality of protrusions and a photodetector. The protrusions are defined by the back-side semiconductor layer, and the photodetector is defined by the front-side semiconductor layer, the absorption enhancement semiconductor layer, and the back-side semiconductor layer.
    Type: Application
    Filed: November 13, 2019
    Publication date: March 12, 2020
    Inventors: Ming-Chi Wu, Chien Nan Tu, Kun-Yu Lin, Shih-Shiung Chen
  • Publication number: 20200083390
    Abstract: An image sensor with an absorption enhancement semiconductor layer is provided. In some embodiments, the image sensor comprises a front-side semiconductor layer, an absorption enhancement semiconductor layer, and a back-side semiconductor layer that are stacked. The absorption enhancement semiconductor layer is stacked between the front-side and back-side semiconductor layers. The absorption enhancement semiconductor layer has an energy bandgap less than that of the front-side semiconductor layer. Further, the image sensor comprises a plurality of protrusions and a photodetector. The protrusions are defined by the back-side semiconductor layer, and the photodetector is defined by the front-side semiconductor layer, the absorption enhancement semiconductor layer, and the back-side semiconductor layer.
    Type: Application
    Filed: November 13, 2019
    Publication date: March 12, 2020
    Inventors: Ming-Chi Wu, Chien Nan Tu, Kun-Yu Lin, Shih-Shiung Chen
  • Publication number: 20200058736
    Abstract: The present disclosure describes a fabrication method that prevents divots during the formation of isolation regions in integrated circuit fabrication. In some embodiments, the method of forming the isolation regions includes depositing a protective layer over a semiconductor layer; patterning the protective layer to expose areas of the semiconductor layer; depositing an oxide on the exposed areas the semiconductor layer and between portions of the patterned protective layer; etching a portion of the patterned protective layer to expose the semiconductor layer; etching the exposed semiconductor layer to form isolation openings in the semiconductor layer; and filling the isolation openings with a dielectric to form the isolation regions.
    Type: Application
    Filed: August 15, 2018
    Publication date: February 20, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Gulbagh Singh, Hsin-Chi Chen, Kun-Tsang Chuang
  • Publication number: 20200051851
    Abstract: The present disclosure describes a fabrication method that can form air-gaps in shallow trench isolation structures (STI) structures. For example, the method includes patterning a semiconductor layer over a substrate to form semiconductor islands and oxidizing the sidewall surfaces of the semiconductor islands to form first liners on the sidewall surfaces. Further, the method includes depositing a second liner over the first liners and the substrate and depositing a first dielectric layer between the semiconductor islands. The second liner between the first dielectric layer and the first liners is removed to form openings between the first dielectric layer and the first liners. A second dielectric layer is deposited over the first dielectric layer to enclose the openings and form air-gaps between the first dielectric layer and the first liners so that the gaps are positioned along the first liners.
    Type: Application
    Filed: October 18, 2019
    Publication date: February 13, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Gulbagh SINGH, Hsin-Chi Chen, Kun-Tsang Chuang
  • Patent number: 10535670
    Abstract: A method of manufacturing a non-volatile memory is described. A substrate including a first region and a second region located at periphery of the first region is provided. A plurality of stacked structures are formed on the first region of the substrate. A wall structure is formed on the second region of the substrate. A conductive layer is formed over the substrate. A bottom anti-reflective coating is formed over the conductive layer. The bottom anti-reflective coating and the conductive layer are etched back. The conductive layer is patterned.
    Type: Grant
    Filed: February 25, 2016
    Date of Patent: January 14, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chien-Hsuan Liu, Chiang-Ming Chuang, Chih-Ming Lee, Kun-Tsang Chuang, Hung-Che Liao, Chia-Ming Pan, Hsin-Chi Chen
  • Patent number: D891504
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: July 28, 2020
    Assignee: TDK TAIWAN CORP.
    Inventors: Fu-Yuan Wu, Kun-Shih Lin, Shang-Yu Hsu, Yi-Ho Chen, Shih-Ting Huang, Shou-Jen Liu, Chien-Lun Huang, Yi-Hsin Nieh, Chen-Chi Kuo, Chia-Pin Hsu, Yu-Huai Liao, Shin-Hua Chen, Yu-Cheng Lin, Shao-Chung Chang, Kuo-Chun Kao, Chia-Hsiu Liu, Chao-Chun Chang, Yuan-Shih Liao
  • Patent number: D902981
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: November 24, 2020
    Assignee: TDK TAIWAN CORP.
    Inventors: Fu-Yuan Wu, Kun-Shih Lin, Shang-Yu Hsu, Yi-Ho Chen, Shih-Ting Huang, Shou-Jen Liu, Chien-Lun Huang, Yi-Hsin Nieh, Chen-Chi Kuo, Chia-Pin Hsu, Yu-Huai Liao, Shin-Hua Chen, Yu-Cheng Lin, Shao-Chung Chang, Kuo-Chun Kao, Chia-Hsiu Liu, Chao-Chun Chang, Yuan-Shih Liao
  • Patent number: D902982
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: November 24, 2020
    Assignee: TDK TAIWAN CORP.
    Inventors: Fu-Yuan Wu, Kun-Shih Lin, Shang-Yu Hsu, Yi-Ho Chen, Shih-Ting Huang, Shou-Jen Liu, Chien-Lun Huang, Yi-Hsin Nieh, Chen-Chi Kuo, Chia-Pin Hsu, Yu-Huai Liao, Shin-Hua Chen, Yu-Cheng Lin, Shao-Chung Chang, Kuo-Chun Kao, Chia-Hsiu Liu, Chao-Chun Chang, Yuan-Shih Liao