Patents by Inventor Kun-Chi Liu

Kun-Chi Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240170489
    Abstract: A circuit includes a base silicon layer, a base oxide layer, a first top silicon layer, a second top silicon layer, a first semiconductor device, and a second semiconductor device. The base oxide layer is formed over the base silicon layer. The first top silicon layer is formed over a first region of the base oxide layer and has a first thickness. The second top silicon layer is formed over a second region of the base oxide layer and has a second thickness less than the first thickness. The first semiconductor device is formed over the first top silicon layer and the second semiconductor device is formed over the second top silicon layer. The ability to fabricate a top silicon layers with differing thicknesses can provide a single substrate having devices with different characteristics, such as having both fully depleted and partially depleted devices on a single substrate.
    Type: Application
    Filed: January 29, 2024
    Publication date: May 23, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Gulbagh Singh, Kuan-Liang Liu, Wang Po-Jen, Kun-Tsang Chuang, Hsin-Chi Chen
  • Publication number: 20240172434
    Abstract: A semiconductor device includes a stacked gate structure, a plurality of stacks and a first conductive layer. The stacks are disposed aside the stacked gate structure and arranged along both a first direction and a second direction perpendicular to the first direction, wherein the stacks are extended continuously along the first direction and segmented in the second direction. The first conductive layer is disposed between segmented portions of the stacks along the second direction, wherein top surfaces of the segmented portions of the stacks are higher than a top surface of the first conductive layer.
    Type: Application
    Filed: January 31, 2024
    Publication date: May 23, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Hsuan Liu, Chiang-Ming Chuang, Chih-Ming Lee, Kun-Tsang Chuang, Hung-Che Liao, Chia-Ming Pan, Hsin-Chi Chen
  • Patent number: 11982866
    Abstract: An optical element driving mechanism is provided and includes a fixed assembly, a movable assembly, a driving assembly and a stopping assembly. The fixed assembly has a main axis. The movable assembly is configured to connect an optical element, and the movable assembly is movable relative to the fixed assembly. The driving assembly is configured to drive the movable assembly to move relative to the fixed assembly. The stopping assembly is configured to limit the movement of the movable assembly relative to the fixed assembly within a range of motion.
    Type: Grant
    Filed: December 15, 2022
    Date of Patent: May 14, 2024
    Assignee: TDK TAIWAN CORP.
    Inventors: Chao-Chang Hu, Liang-Ting Ho, Chen-Er Hsu, Yi-Liang Chan, Fu-Lai Tseng, Fu-Yuan Wu, Chen-Chi Kuo, Ying-Jen Wang, Wei-Han Hsia, Yi-Hsin Tseng, Wen-Chang Lin, Chun-Chia Liao, Shou-Jen Liu, Chao-Chun Chang, Yi-Chieh Lin, Shang-Yu Hsu, Yu-Huai Liao, Shih-Wei Hung, Sin-Hong Lin, Kun-Shih Lin, Yu-Cheng Lin, Wen-Yen Huang, Wei-Jhe Shen, Chih-Shiang Wu, Sin-Jhong Song, Che-Hsiang Chiu, Sheng-Chang Lin
  • Patent number: 11925017
    Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, a stacked gate structure, and a wall structure. The stacked gate structure is on the substrate and extending along a first direction. The wall structure is on the substrate and laterally aside the stacked gate structure. The wall structure extends along the first direction and a second direction perpendicular to the first direction. The stacked gate structure is overlapped with the wall structure in the first direction and the second direction.
    Type: Grant
    Filed: January 13, 2020
    Date of Patent: March 5, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Hsuan Liu, Chiang-Ming Chuang, Chih-Ming Lee, Kun-Tsang Chuang, Hung-Che Liao, Chia-Ming Pan, Hsin-Chi Chen
  • Patent number: 8103494
    Abstract: A management system and method. The system comprises at least one delivery request, a plurality of equipment and a simulator. The delivery request indicates a plurality of devices, each comprising a respective quantity. The equipment tests the devices, each equipment comprising an equipment configuration. The simulator retrieves device configuration requirements of respective devices, maps the devices to the equipment according to the respective device configuration requirements and the equipment configurations to obtain a mapping result, and calculates at least one performance index based on the mapping result and the quantity of respective devices.
    Type: Grant
    Filed: December 2, 2005
    Date of Patent: January 24, 2012
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Derek Wang, Kun-Chi Liu, Ta-Chin Lin
  • Publication number: 20070128892
    Abstract: A management system and method. The system comprises at least one delivery request, a plurality of equipment and a simulator. The delivery request indicates a plurality of devices, each comprising a respective quantity. The equipment tests the devices, each equipment comprising an equipment configuration. The simulator retrieves device configuration requirements of respective devices, maps the devices to the equipment according to the respective device configuration requirements and the equipment configurations to obtain a mapping result, and calculates at least one performance index based on the mapping result and the quantity of respective devices.
    Type: Application
    Filed: December 2, 2005
    Publication date: June 7, 2007
    Inventors: Derek Wang, Kun-Chi Liu, Ta-Chin Lin
  • Patent number: 7142938
    Abstract: A manufacturing management system and method. The system includes a manufacturing execution system and a plurality of manufacturing sites coupled to the manufacturing execution system. The manufacturing execution system comprises management data to support the manufacturing sites. Each manufacturing site comprises a corresponding site attribute. At least one of the manufacturing sites receives a lot, queries the management data for the lot from the manufacturing execution system according to lot identification and the site attribute of the manufacturing site receiving the lot, and processes the lot accordingly.
    Type: Grant
    Filed: October 13, 2004
    Date of Patent: November 28, 2006
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shiaw-Lin Chi, Kun-Chi Liu, Chien-Wei Wang, Chih-Chien Chang, Chang-Hsi Lin, Chien-Fei Cheng, Lieh-Jung Chen, Fang-Ni Wu, Birgie Kuo, Yi-Fang Su
  • Publication number: 20060079978
    Abstract: A manufacturing management system and method. The system includes a manufacturing execution system and a plurality of manufacturing sites coupled to the manufacturing execution system. The manufacturing execution system comprises management data to support the manufacturing sites. Each manufacturing site comprises a corresponding site attribute. At least one of the manufacturing sites receives a lot, queries the management data for the lot from the manufacturing execution system according to lot identification and the site attribute of the manufacturing site receiving the lot, and processes the lot accordingly.
    Type: Application
    Filed: October 13, 2004
    Publication date: April 13, 2006
    Inventors: Shiaw-Lin Chi, Kun-Chi Liu, Chien-Wei Wang, Chih-Chien Chang, Chang-Hsi Lin, Chien-Fei Cheng, Lieh-Jung Chen, Fang-Ni Wu, Birgie Kuo, Yi-Fang Su