Abstract: Disclosed is a wafer level testing method for testing a plurality of singulated 3D-stacked chip cubes by utilizing adjustable wafer maps to adjust the pick-and-place positions of the cubes on a carrier wafer. The wafer maps have a plurality of probe-card activated regions each including a plurality of component-attaching regions. Two wafer-level testing steps are performed on the cubes disposed on the carrier wafer according to the wafer maps. By analyzing the electrical testing results of the trial-run wafer-level testing step from the original wafer map, some prone-to-overkill component-attaching regions are confirmed and to create a corrected wafer map which the prone-to-overkill component-attaching regions are excluded from probe-card activated regions. Then, according to the corrected wafer map, cubes are disposed on the carrier wafer without disposing in the prone-to-overkill component-attaching regions.

Abstract: Disclosed is a wafer level testing method for testing a plurality of singulated 3D-stacked chip cubes by utilizing adjustable wafer maps to adjust the pick-and-place positions of the cubes on a carrier wafer. The wafer maps have a plurality of probe-card activated regions each including a plurality of component-attaching regions. Two wafer-level testing steps are performed on the cubes disposed on the carrier wafer according to the wafer maps. By analyzing the electrical testing results of the trial-run wafer-level testing step from the original wafer map, some prone-to-overkill component-attaching regions are confirmed and to create a corrected wafer map which the prone-to-overkill component-attaching regions are excluded from probe-card activated regions. Then, according to the corrected wafer map, cubes are disposed on the carrier wafer without disposing in the prone-to-overkill component-attaching regions.

Abstract: Disclosed is a method for wafer-level testing a plurality of diced multi-chip stacked packages. Each package includes a plurality of chips with vertically electrical connections such as TSVs. Next, according to a die-on-wafer array arrangement, the multi-chip stacked packages are fixed on a transparent reconstructed wafer by a photo-sensitive adhesive, and the packages are located within the component-bonding area of the wafer. Then, the transparent reconstructed wafer carrying the multi-chip stacked packages can be loaded into a wafer tester for probing. Accordingly, the wafer testing probers in the wafer tester can be utilized to probe the testing electrodes of the stacked packages so that it is easy to integrate this wafer-level testing method especially into TSV packaging processes.