Abstract: An air-floating guide rail device includes a guide rail unit, a slider unit, and a linear motor unit. The guide rail unit includes a guide rail body and two air-floating block sets made of a material different from that of the guide rail body and each including top and side air-floating blocks. The slider unit includes a main sliding seat and two lateral sliding seats connected integrally to the main sliding seat and each having first and second guiding surfaces transverse to each other and disposed respectively adjacent to corresponding top and side air-floating blocks, and first and second air guiding passages connecting the first and second guiding surfaces to the external environment. The linear motor unit includes a stator and a mover mounted fixedly to the main sliding seat and movable relative to the stator for driving linear movement of the slider unit relative to the guide rail unit.

Abstract: A solar cell includes a semiconductor substrate, a passivation layer, a back electrode layer, and several bus bars. The semiconductor substrate has an upper surface and a lower surface opposite with each other. The passivation layer is disposed at the lower surface and includes several blank regions and several first openings. Each first opening is not located in the blank regions. The bus bars are respectively disposed on the blank regions of the passivation layer. The back electrode layer is disposed on the passivation layer and electrically connected to the semiconductor substrate through the first openings. The back electrode layer includes several second openings corresponding to the bus bars, respectively. The size of each second opening is not greater than the size of the corresponding bus bar, so that the back electrode layer is electrically connected to the bus bars.

Abstract: One aspect of the present invention relates to a photovoltaic cell. In one embodiment, the photovoltaic cell includes a first conductive layer, an N-doped semiconductor layer formed on the first conductive layer, a first silicon layer formed on the N-doped semiconductor layer, a nanocrystalline silicon (nc-Si) layer formed on a first silicon layer, a second silicon layer formed on the nc-Si layer, a P-doped semiconductor layer on the second silicon layer, and a second conductive layer formed on the P-doped semiconductor layer, where one of the first silicon layer and the second silicon layer is formed of amorphous silicon, and the other of the first silicon layer and the second silicon layer formed of polycrystalline silicon.

Abstract: A solar cell includes a semiconductor substrate, a passivation layer, a back electrode layer, and several bus bars. The semiconductor substrate has an upper surface and a lower surface opposite with each other. The passivation layer is disposed at the lower surface and includes several blank regions and several first openings. Each first opening is not located in the blank regions. The bus bars are respectively disposed on the blank regions of the passivation layer. The back electrode layer is disposed on the passivation layer and electrically connected to the semiconductor substrate through the first openings. The back electrode layer includes several second openings corresponding to the bus bars, respectively. The size of each second opening is not greater than the size of the corresponding bus bar, so that the back electrode layer is electrically connected to the bus bars.

Abstract: A solar cell includes a crystalline silicon semiconductor substrate, an intrinsic amorphous silicon semiconductor layer, an amorphous silicon semiconductor layer and a transparent conductive layer. The crystalline silicon semiconductor substrate possesses a first doped type and a trench is formed thereon to form an enclosed area to define a first electrode region in the enclosed area and a second electrode region out of the enclosed area. The intrinsic amorphous silicon semiconductor layer, the amorphous silicon semiconductor layer and the transparent conductive layer are formed sequentially on the crystalline silicon semiconductor substrate and in the trench. Having discontinuity in the trench, the amorphous silicon semiconductor layer, the amorphous silicon semiconductor layer and the transparent conductive layer provide an isolation function between the previously defined first and second electrode regions.

Abstract: A capacitance difference detecting circuit with a control circuit, a first capacitor, a second capacitor, a voltage control unit and a computing device. The control circuit generates a control signal according to a first voltage and a second voltage. The voltage control unit cooperates with the first capacitor to be detected and the second capacitor to be detected, according to the control signal, to generate the first voltage and the second voltage. The computing device computes a capacitance difference between the first capacitor to be detected and the second capacitor to be detected according to the first voltage, the second voltage and a parameter of the voltage control unit.

Abstract: A solar cell includes a crystalline silicon semiconductor substrate, an intrinsic amorphous silicon semiconductor layer, an amorphous silicon semiconductor layer and a transparent conductive layer. The crystalline silicon semiconductor substrate possesses a first doped type and a trench is formed thereon to form an enclosed area to define a first electrode region in the enclosed area and a second electrode region out of the enclosed area. The intrinsic amorphous silicon semiconductor layer, the amorphous silicon semiconductor layer and the transparent conductive layer are formed sequentially on the crystalline silicon semiconductor substrate and in the trench. Having discontinuity in the trench, the amorphous silicon semiconductor layer, the amorphous silicon semiconductor layer and the transparent conductive layer provide an isolation function between the previously defined first and second electrode regions.

Abstract: A back-contact solar cell and manufacturing method thereof includes steps of providing a substrate, forming a first conductive doping region and a second conductive doping region on the substrate, forming a passivation layer on the substrate to cover the first conductive doping region and the second conductive doping region, distantly disposing a plurality of first electrode paste clusters on the passivation layer, in which each first electrode paste cluster corresponds to the first conductive doping region and the second conductive doping region and includes a metal component and a glass component, enclosing the first electrode paste cluster by a plurality of second electrode pastes, and heating at least the first electrode paste clusters to an predetermined temperature so that the metal component, the metal component and the passivation layer contacted by the first electrode paste clusters forms a plurality of contacting regions.

Abstract: A method for fabricating a TFT array substrate including the following steps is provided. A substrate having a pixel region and a photosensitive region is provided. A first patterned conductive layer is formed on the substrate, wherein the first patterned conductive layer includes a gate electrode disposed in the pixel region and a first electrode disposed in the photosensitive region, and a photosensitive dielectric layer is formed on the first electrode. A gate insulation layer is formed to cover the gate electrode, the photosensitive dielectric layer and the first electrode. A patterned semiconductor layer is formed on the gate insulation layer above the gate electrode. A source electrode and a drain electrode are formed on the patterned semiconductor layer at two sides of the gate electrode, wherein the gate electrode, the source electrode, and the drain electrode constitute a TFT. A second electrode is formed on the photosensitive dielectric layer.

Abstract: A manufacturing method of a thin film transistor array substrate is provided. In the method, a substrate having a display region and a sensing region is provided. At least a display thin film transistor is formed in the display region, a first sensing electrode is formed in the sensing region, and an inter-layer dielectric layer is disposed on the substrate, covers the display thin film transistor, and exposes the first sensing electrode. A patterned photo sensitive dielectric layer is then formed on the first sensing electrode. A patterned transparent conductive layer is subsequently formed on the substrate, wherein the patterned transparent conductive layer includes a pixel electrode coupled to the corresponding display thin film transistor and includes a second sensing electrode located on the patterned photo sensitive dielectric layer. A manufacturing method of a liquid crystal display panel adopting the aforementioned thin film transistor array substrate is also provided.

Abstract: A method of forming an optical sensor includes the following steps. A substrate is provided, and a read-out device is formed on the substrate. a first electrode electrically connected to the read-out device is formed on the substrate. a photosensitive silicon-rich dielectric layer is formed on the first electrode, wherein the photosensitive silicon-rich dielectric layer comprises a plurality of nanocrystalline silicon crystals. A second electrode is formed on the photosensitive silicon-rich dielectric layer.

Abstract: A capacitance difference detecting method, comprising: (a) utilizing a voltage control unit to cooperate with a first capacitor to be detected and a second capacitor to be detected to generate a first voltage and a second voltage; and (b) computing a capacitance difference between the first capacitor to be detected and the second capacitor to be detected according to the first voltage, the second voltage and a parameter of the voltage control unit.

Abstract: A capacitance difference detecting circuit, which comprises: a control circuit, for generating a control signal according to a first voltage and a second voltage; a first capacitor to be detected; a second capacitor to be detected; a voltage control unit, for cooperating with the first capacitor to be detected and the second capacitor to be detected, according to the control signal, to generate the first voltage and the second voltage; and a computing device, for computing a capacitance difference between the first capacitor to be detected and the second capacitor to be detected according to the first voltage, the second voltage and a parameter of the voltage control unit.

Abstract: In one aspect of the present invention, a photovoltaic module includes a plurality of sub-modules. Each sub-module includes a plurality of photovoltaic cells spatially arranged as an array, each cell having first and second conductive layers sandwiching an active layer therebetween. The cells in each sub-module are electrically connected to each other in series. Each sub-module further includes positive and negative electrodes formed on the second conductive layers of the first and last cells, respectively, in a respective sub-module. The positive electrode of each sub-module is electrically connected to each other and the negative electrode of each sub-module is electrically connected to each other such that the plurality of sub-modules is electrically connected in parallel. The plurality of sub-modules is spatially arranged next to each other as an array such that at least one sub-module is spatially separated from its immediately next sub-module by a gap.

Abstract: A capacitance difference detecting circuit includes a control circuit, for generating a control signal according to a first voltage and a second voltage; a first capacitor to be detected; a second capacitor to be detected; a first constant capacitor, having a terminal coupled to the first terminal of the first capacitor to be detected and the first input terminal; a second constant capacitor, having a terminal coupled to the first terminal of the second capacitor to be detected and the second input terminal; a voltage control unit, cooperating with the first capacitor to be detected, the second capacitor to be detected, the first constant capacitor and the second constant capacitor to control the first voltage and the second voltage. The voltage control unit is an adjustable capacitor and a capacitance value of the adjustable capacitor is controlled by the control signal.

Abstract: In one aspect of the present invention, a photovoltaic panel includes a substrate, a reflective layer formed on the substrate, a first conductive layer formed on the reflective layer, an active layer formed on the first conductive layer, and a second conductive layer formed on the active layer. The reflective layer has an index of refraction and a thickness such that the reflectance spectrum of the photovoltaic device for light incident on the substrate has a maximum in a selected wavelength range in the visible spectrum.

Abstract: An optical reflective touch panel and pixels and a system thereof are provided. Each pixel of the optical reflective touch panel includes a display circuit and a sensing circuit. The display circuit controls the display of the pixel. The sensing circuit is coupled to the display circuit for sensing a sensitization state of the pixel during a turned-on period and a turned-off period of a backlight module and outputting a digital signal to notify an optical reflective touch panel system that whether the pixel is touched or not.

Abstract: A buffer layer for promoting electron mobility. The buffer layer comprises amorphous silicon layer (a-Si) and an oxide-containing layer. The a-Si has high enough density that the particles in the substrate are prevented by the a-Si buffer layer from diffusing into the active layer. As well, the buffer, having thermal conductivity, provides a good path for thermal diffusion during the amorphous active layer's recrystallization by excimer laser annealing (ELA). Thus, the uniformity of the grain size of the crystallized silicon is improved, and electron mobility of the TFT is enhanced.

Abstract: A thin-film solar cell includes a body and a polymer layer. The body includes a first electrode layer, a photoelectric conversion layer, and a second electrode layer, and the polymer layer includes a hardening material and an interface material. The photoelectric conversion layer is disposed between the first electrode layer and the second electrode layer, and the polymer layer surrounds the photoelectric conversion layer, in which the interface material is used for bonding to the hardening material and the photoelectric conversion layer respectively. Therefore, the thin-film solar cell may reduce the Staebler-Wronski Effect generated by the photoelectric conversion layer in the photoelectric conversion procedure. Accordingly, the photoelectric conversion efficiency is improved.