Abstract: A neural network is used to place macros on a chip canvas in an integrated circuit (IC) design. The macros are first clustered into multiple macro clusters. Then the neural network generates a probability distribution over locations on a grid and aspect ratios of a macro cluster. The grid represents the chip canvas and is formed by rows and columns of grid cells. The macro cluster is described by at least an area size, aspect ratios, and wire connections. Action masks are generated for respective ones of the aspect ratios to block out a subset of unoccupied grid cells based on design rules that optimize macro placement. Then, by applying the action masks on the probability distribution, a masked probability distribution is generated. Based on the masked probability distribution, a location on the grid is selected for placing the macro cluster with a chosen aspect ratio.

Abstract: A testable circuit includes a first function logic, an input output cell including an input/output unit and a first control multiplexer; and a first testing block is provided, wherein the input/output unit has at least a connection terminal. The first control multiplexer has an output port coupled to the connection terminal, a first input port coupled to the first functional logic, and a second input port. The first testing block is coupled between the first functional logic and the second input port, wherein when the testable circuit is under a testing mode, the first control multiplexer couples the second input port to the output port; and when the testable circuit is under a normal mode, the first control multiplexer couples the first input port to the output port.