Patents by Inventor Kun-Dae Yeom

Kun-Dae Yeom has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10607905
    Abstract: A semiconductor package includes a package substrate including at least one through-hole in a chip mounting region, a plurality of wiring patterns at a top surface of the package substrate. The wiring patterns include respective extension portions and respective landing pads. At least some of the landing pads obliquely extend toward the through-hole. Conductive bumps are formed on corresponding landing pads to connect to a semiconductor chip mounted on the chip mounting region of the package substrate. A molding material extends between the top surface of the package substrate and the semiconductor chip and fills the through-hole.
    Type: Grant
    Filed: June 14, 2019
    Date of Patent: March 31, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Baek Ki, Tark-Hyun Ko, Kun-Dae Yeom, Yong-Kwan Lee, Keun-Ho Jang
  • Publication number: 20190295909
    Abstract: A semiconductor package includes a package substrate including at least one through-hole in a chip mounting region, a plurality of wiring patterns at a top surface of the package substrate. The wiring patterns include respective extension portions and respective landing pads. At least some of the landing pads obliquely extend toward the through-hole. Conductive bumps are formed on corresponding landing pads to connect to a semiconductor chip mounted on the chip mounting region of the package substrate. A molding material extends between the top surface of the package substrate and the semiconductor chip and fills the through-hole.
    Type: Application
    Filed: June 14, 2019
    Publication date: September 26, 2019
    Inventors: Baek KI, Tark-Hyun KO, Kun-Dae YEOM, Yong-Kwan LEE, Keun-Ho JANG, Sang Jin HYUN
  • Patent number: 10361135
    Abstract: A semiconductor package includes a package substrate including at least one through-hole in a chip mounting region, a plurality of wiring patterns at a top surface of the package substrate. The wiring patterns include respective extension portions and respective landing pads. At least some of the landing pads obliquely extend toward the through-hole. Conductive bumps are formed on corresponding landing pads to connect to a semiconductor chip mounted on the chip mounting region of the package substrate. A molding material extends between the top surface of the package substrate and the semiconductor chip and fills the through-hole.
    Type: Grant
    Filed: July 4, 2017
    Date of Patent: July 23, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Baek Ki, Tark-Hyun Ko, Kun-Dae Yeom, Yong-Kwan Lee, Keun-Ho Jang
  • Publication number: 20180076105
    Abstract: A semiconductor package includes a package substrate including at least one through-hole in a chip mounting region, a plurality of wiring patterns at a top surface of the package substrate. The wiring patterns include respective extension portions and respective landing pads. At least some of the landing pads obliquely extend toward the through-hole. Conductive bumps are formed on corresponding landing pads to connect to a semiconductor chip mounted on the chip mounting region of the package substrate. A molding material extends between the top surface of the package substrate and the semiconductor chip and fills the through-hole.
    Type: Application
    Filed: July 4, 2017
    Publication date: March 15, 2018
    Inventors: Baek KI, Tark-Hyun KO, Kun-Dae YEOM, Yong-Kwan LEE, Keun-Ho JANG
  • Patent number: 9455217
    Abstract: Provided is a semiconductor package including multiple semiconductor chips, and separate groups of leads connected to the semiconductor chips. The leads are exposed to the outside of the semiconductor package. The plurality of leads may include a first lead group for a first chip group and a second lead group for a second chip group. The first and second chip groups are part of the package.
    Type: Grant
    Filed: October 30, 2014
    Date of Patent: September 27, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Chul Park, Hyeong-seob Kim, Kun-dae Yeom, Gwang-man Lim
  • Patent number: 9041181
    Abstract: A land grid array (LGA) package including a substrate having a plurality of lands formed on a first surface of the substrate, a semiconductor chip mounted on a second surface of the substrate, a connection portion connecting the semiconductor chip and the substrate, and a support layer formed on part of a surface of a first land.
    Type: Grant
    Filed: February 10, 2011
    Date of Patent: May 26, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hee-chul Lee, Myung-kee Chung, Kun-dae Yeom
  • Publication number: 20150054144
    Abstract: Provided sa a semiconductor package including multiple semiconductor chips, and separate groups of leads connected to the semiconductor chips. The leads are exposed to the outside of the semiconductor package. The plurality of leads may include a first lead group for a first chip group and a second lead group for a second chip group. The first and second chip groups are part of the package.
    Type: Application
    Filed: October 30, 2014
    Publication date: February 26, 2015
    Inventors: Chul Park, Hyeong-seob Kim, Kun-dae Yeom, Gwang-man Lim
  • Patent number: 8901750
    Abstract: Provided is a semiconductor package including multiple semiconductor chips, and separate groups of leads connected to the semiconductor chips. The leads are exposed to the outside of the semiconductor package. The plurality of leads may include a first lead group for a first chip group and a second lead group for a second chip group. The first and second chip groups are part of the package.
    Type: Grant
    Filed: April 11, 2014
    Date of Patent: December 2, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chul Park, Hyeong-seob Kim, Kun-dae Yeom, Gwang-man Lim
  • Publication number: 20140225281
    Abstract: Provided is a semiconductor package including multiple semiconductor chips, and separate groups of leads connected to the semiconductor chips. The leads are exposed to the outside of the semiconductor package. The plurality of leads may include a first lead group for a first chip group and a second lead group for a second chip group. The first and second chip groups are part of the package.
    Type: Application
    Filed: April 11, 2014
    Publication date: August 14, 2014
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Chul Park, Hyeong-seob Kim, Kun-dae Yeom, Gwang-man Lim
  • Patent number: 8723333
    Abstract: Provided is a semiconductor package including multiple semiconductor chips, and separate groups of leads connected to the semiconductor chips. The leads are exposed to the outside of the semiconductor package. The plurality of leads may include a first lead group for a first chip group and a second lead group for a second chip group. The first and second chip groups are part of the package.
    Type: Grant
    Filed: May 7, 2012
    Date of Patent: May 13, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chul Park, Hysong-seob Kim, Kun-dae Yeom, Gwang-man Lim
  • Patent number: 8664757
    Abstract: A semiconductor package including a protection layer, a plurality of semiconductor chips stacked on the protection layer, an inner encapsulant disposed on the protection layer to surround side surfaces of the semiconductor chips, and a terminal disposed to be buried in an upper portion of the inner encapsulant. Herein, each of the semiconductor chips includes an active surface, an inactive surface opposite to the active surface, and a chip pad disposed on a portion of the active surface, and an upper surface of the terminal is exposed from an upper surface of the inner encapsulant.
    Type: Grant
    Filed: June 17, 2011
    Date of Patent: March 4, 2014
    Assignee: SAMSUNG Electronics Co., Ltd.
    Inventors: Yun-Rae Cho, Kun-Dae Yeom
  • Publication number: 20130161836
    Abstract: Provided is a semiconductor package comprising a substrate, a semiconductor chip formed on the substrate, and an interposer including a plurality of segments which are separated from each other and arranged on the substrate to surround the semiconductor chip. And a stacked package for multiple chips including the semiconductor package with a plurality of segments of an interposer is provided.
    Type: Application
    Filed: August 13, 2012
    Publication date: June 27, 2013
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kun-Dae YEOM, Young-Min KIM, Jong-Bo SHIM, Woo-Dong LEE
  • Publication number: 20120217656
    Abstract: Provided is a semiconductor package including multiple semiconductor chips, and separate groups of leads connected to the semiconductor chips. The leads are exposed to the outside of the semiconductor package. The plurality of leads may include a first lead group for a first chip group and a second lead group for a second chip group. The first and second chip groups are part of the package.
    Type: Application
    Filed: May 7, 2012
    Publication date: August 30, 2012
    Inventors: Chul Park, Hysong-seob Kim, Kun-dae Yeom, Gwang-man Lim
  • Patent number: 8193626
    Abstract: Provided is a semiconductor package including multiple semiconductor chips, and separate groups of leads connected to the semiconductor chips. The leads are exposed to the outside of the semiconductor package. The plurality of leads may include a first lead group for a first chip group and a second lead group for a second chip group. The first and second chip groups are part of the package.
    Type: Grant
    Filed: December 3, 2009
    Date of Patent: June 5, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chul Park, Hysong-seob Kim, Kun-dae Yeom, Gwang-man Lim
  • Publication number: 20120007227
    Abstract: A semiconductor package including a protection layer, a plurality of semiconductor chips stacked on the protection layer, an inner encapsulant disposed on the protection layer to surround side surfaces of the semiconductor chips, and a terminal disposed to be buried in an upper portion of the inner encapsulant. Herein, each of the semiconductor chips includes an active surface, an inactive surface opposite to the active surface, and a chip pad disposed on a portion of the active surface, and an upper surface of the terminal is exposed from an upper surface of the inner encapsulant.
    Type: Application
    Filed: June 17, 2011
    Publication date: January 12, 2012
    Applicant: Samsung Electronics Co., Ltd
    Inventors: Yun-Rae CHO, Kun-Dae Yeom
  • Publication number: 20110304056
    Abstract: A stack-type semiconductor package includes: a substrate; a first through electrode module stacked on the substrate comprising a first chip and a second chip connected to the first chip by a first through electrode; a second through electrode module stacked on the first through electrode comprising a third chip and a fourth chip connected to the third chip by a second through electrode; and a signal transmission medium for electrically connecting the substrate to the first through electrode module and the second through electrode module. The stack-type semiconductor package may be highly integrated, reliability thereof is improved by increasing strength of the chips, stacking in high-steps is possible, the stack-type semiconductor package may be thin and simple, and productivity thereof may be significantly increased.
    Type: Application
    Filed: June 13, 2011
    Publication date: December 15, 2011
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dong-hun Lee, Hyung-gil Baek, Kun-dae Yeom
  • Publication number: 20110198744
    Abstract: A land grid array (LGA) package including a substrate having a plurality of lands formed on a first surface of the substrate, a semiconductor chip mounted on a second surface of the substrate, a connection portion connecting the semiconductor chip and the substrate, and a support layer formed on part of a surface of a first land.
    Type: Application
    Filed: February 10, 2011
    Publication date: August 18, 2011
    Inventors: Hee-chul Lee, Myung-kee Chung, Kun-dae Yeom
  • Publication number: 20100314740
    Abstract: A multi-chip package device can include a plurality of integrated circuit device chips stacked on one another inside a multi-chip package including the device. The device can include an electrically isolated multi-chip support structure that is directly connected to first and second electrically active integrated circuit structures via respective first and second adhesive layers located on opposing sides of the electrically isolated multi-chip support structure.
    Type: Application
    Filed: May 10, 2010
    Publication date: December 16, 2010
    Inventors: Keun-ho CHOI, Myung-kee CHUNG, Kun-dae YEOM, Kil-soo KIM
  • Patent number: 7759795
    Abstract: Provided is a printed circuit board having a bump interconnection structure that improves reliability between interconnection layers. Also provided is a method of fabricating the printed circuit board and semiconductor package using the printed circuit board. According to one embodiment, the printed circuit board includes a plurality of bumps formed on a resin layer between a first interconnection layer and a second interconnection layer. The second interconnection layer includes insertion holes corresponding to upper portions of the bumps so that the upper portions of the bumps protrude from the second interconnection layer. The upper portion of at least one of the bumps includes a rivet portion having a diameter greater that the diameter of the corresponding insertion hole to reliably interconnect the first and second interconnection layers.
    Type: Grant
    Filed: September 5, 2007
    Date of Patent: July 20, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-Lyong Kim, Young-Shin Choi, Jong-Gi Lee, Kun-Dae Yeom, Chul-Yong Jang, Hyun-Jong Woo
  • Publication number: 20100117217
    Abstract: Provided is a semiconductor package including multiple semiconductor chips, and separate groups of leads connected to the semiconductor chips. The leads are exposed to the outside of the semiconductor package. The plurality of leads may include a first lead group for a first chip group and a second lead group for a second chip group. The first and second chip groups are part of the package.
    Type: Application
    Filed: December 3, 2009
    Publication date: May 13, 2010
    Inventors: Chul Park, Hysong-seob Kim, Kun-dae Yeom, Gwang-man Lim