Abstract: System and method for securely waking a computer system over a network. A registration message may be received by a server from a network interface controller (NIC) in a first computer system over a network. The first computer system may be in a sleep mode. The first computer system may be registered by the server: identification information for the first computer system may be stored in a memory. A wakeup message may be received from a second computer system over the network. The wakeup message may include information identifying the first computer system and authentication information. The wakeup message may be sent to the first computer system over the network. The wakeup message may indicate to the NIC to wake up the first computer system. The authentication information may be authenticated by either or both of the server or the NIC prior to waking up the first computer system.

Abstract: A physical configuration of a computer system is described. The motherboard has a first series of I/O ports at an edge thereof. A riser card is perpendicularly connected with the motherboard, wherein the riser card has a second series of I/O ports at an edge thereof. A housing encloses the motherboard and the riser card, wherein the housing has a plurality of openings, exposing each of the first series of I/O ports and the second series of I/O ports so as to form an L-shaped I/O port area on a flat surface thereof.

Abstract: A PCI-E automatic allocation system which essentially consists of a detection module and a switch module, wherein the detection module detects the states of the logic signals on the ground pins of a first PCI-E slot with large lane width and a second PCI-E slot with small lane width in a computer system, to determine whether the first and second PCI-E slots hold any inserted expansion card; if the detection module detects an inserted expansion card in the first PCI-E slot rather than the second PCI-E slot, a switch control signal output is generated, to control the switch operation performed by the switch module, that is, transferring lane availability from the second PCI-E slot to the first PCI-E slot, with a view to enhancing the use of PCI-E lanes, speeding up data transmission, and overcoming a known drawback of PCI-E buses, that is, inflexible design.

Abstract: A physical configuration of a computer system is described. The motherboard has a first series of I/O ports at an edge thereof. A riser card is perpendicularly connected with the motherboard, wherein the riser card has a second series of I/O ports at an edge thereof. A housing encloses the motherboard and the riser card, wherein the housing has a plurality of openings, exposing each of the first series of I/O ports and the second series of I/O ports so as to form an L-shaped I/O port area on a flat surface thereof.

Abstract: A device recognition circuit for initiating a computer system includes an adapter module and a control module. The adapter module is capable of connecting a peripheral interface card the adapter module having I/O ports, the I/O ports carry present signals generated by the adapter module. The control module having general purpose input/output (GPIO) pins for receiving the present signals, wherein the control module determines an expansion type of the adapter module according to the present signals. The embodiment of present invention also provides a method of recognizing a device for initiating a computer system.

Abstract: A power switching circuit includes a flip-flop for receiving an abnormal power-off signal output by shutdown software of an electronic device, and outputting a trigger signal when a power supply of the electronic device is in an abnormal shutdown status and the abnormal power-off signal. The power switching circuit further includes a switching device for receiving a first control signal indicating that the backup battery is providing power and a second control signal indicating that the power supply is providing power, and outputting a backup battery power supply signal when the abnormal power-off signal is transmitted from the flip-flop or a power supply signal when the abnormal power-off signal is not transmitted from the output end of the flip-flop. The power switching circuit further includes a voltage regulator device for switching the backup battery or a power supply to provide power.

Abstract: A PCI-E automatic allocation system which essentially consists of a detection module and a switch module, wherein the detection module detects the states of the logic signals on the ground pins of a first PCI-E slot with large lane width and a second PCI-E slot with small lane width in a computer system, to determine whether the first and second PCI-E slots hold any inserted expansion card; if the detection module detects an inserted expansion card in the first PCI-E slot rather than the second PCI-E slot, a switch control signal output is generated, to control the switch operation performed by the switch module, that is, transferring lane availability from the second PCI-E slot to the first PCI-E slot, with a view to enhancing the use of PCI-E lanes, speeding up data transmission, and overcoming a known drawback of PCI-E buses, that is, inflexible design.

Abstract: A modularized circuit board bus connection control method and system is proposed, which is designed for use with a computer platform, such as a blade server, for providing a bus connection control function when connected to a modularized circuit board, such as a server module; which is characterized by the capability of using an enable signal activating voltage from a built-in enablement setting circuit in the blade server for bus connection control, such that if the server module is well electrically connected to the blade server, the bus will be switched to a connected state; and otherwise, if poorly connected, the bus will be maintained in the disconnected state to isolate the server module from the blade server. This feature can help prevent the blade server to waste much time and system resource in handling the condition of poor electrical connection and thus ensure the overall system performance.