Patents by Inventor Kun-Han Lee

Kun-Han Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11942542
    Abstract: A semiconductor device includes a substrate, a gate dielectric layer, a gate electrode, a field plate, a source electrode and a drain electrode. The gate dielectric layer is disposed on the substrate and includes a first portion having a first thickness, a second portion having a second thickness, and a third portion having a third thickness. The first, second and third thicknesses are different from each other, and the first thickness is smaller than the second and third thicknesses. The gate electrode is disposed on the first portion of the gate dielectric layer. The field plate is separated from and electrically coupled to the gate electrode, and is disposed on the second and third portions of the gate dielectric layer. The source and drain electrodes are disposed on the sides of the gate electrode and the field plate, respectively.
    Type: Grant
    Filed: September 29, 2021
    Date of Patent: March 26, 2024
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Syed-Sarwar Imam, Chia-Hao Lee, Chih-Hung Lin, Kun-Han Lin
  • Publication number: 20240072571
    Abstract: A wireless transmission module for transmitting energy or signals includes a first magnetically conductive element, a first coil assembly and a first adhesive element. The first coil assembly and the first magnetically conductive element are arranged along a main axis. The first adhesive element is configured to be adhered to the first coil assembly and the first magnetic conductive element. The first adhesive element is disposed between the first coil assembly and the first magnetically conductive element.
    Type: Application
    Filed: December 16, 2022
    Publication date: February 29, 2024
    Inventors: Feng-Lung CHIEN, Mao-Chun CHEN, Kun-Ying LEE, Yuan HAN, Tsang-Feng WU
  • Publication number: 20230154631
    Abstract: A method and an apparatus are provided for performing a fusion reaction. The method comprises providing neutral gas within a gas chamber, supplying energy to the gas chamber to initiate heating of a cathode and ionization of the neutral gas into protons and electrons, causing formation of a conducting channel due to the ionized neutral gas, causing formation of an electron layer outside the cathode based on set of thermionically emitted electrons by the heated cathode, causing acceleration of the electrons towards the cathode to cause the heated cathode to emit a set of secondary electrons due to a potential associated with the electron layer. The set of secondary electrons enhance strength of the electron layer. The method comprises causing formation of an electrostatic potential profile with dips and peaks, due to an electron-ion two-stream instability. The protons are accelerated towards the cathode at peaks and bombardment of the protons into the cathode enables fusion reaction.
    Type: Application
    Filed: October 7, 2022
    Publication date: May 18, 2023
    Inventors: Luo-Chuang LEE, Kun-Han LEE, Dongdong NI
  • Patent number: 6320415
    Abstract: A CMOS input/output control circuit capable of operating normally under different input voltages such as 2.5 V, 3.3 V and 5 V. Moreover, the PMOS transistor inside the n-well region is shut by a gate control circuit and an n-well control circuit of this invention when a 5 V input voltage is applied to the circuit.
    Type: Grant
    Filed: April 3, 2000
    Date of Patent: November 20, 2001
    Assignee: United Microelectronics Corp.
    Inventor: Kun-Han Lee