Patents by Inventor Kun-Han Tsai
Kun-Han Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11923205Abstract: A method for manufacturing a semiconductor device includes: providing a wafer-bonding stack structure having a sidewall layer and an exposed first component layer; forming a photoresist layer on the first component layer; performing an edge trimming process to at least remove the sidewall layer; and removing the photoresist layer. In this way, contaminant particles generated from the blade during the edge trimming process may fall on the photoresist layer but not fall on the first component layer, so as to protect the first component layer from being contaminated.Type: GrantFiled: December 17, 2021Date of Patent: March 5, 2024Assignee: UNITED MICROELECTRONICS CORPORATIONInventors: Kun-Ju Li, Ang Chan, Hsin-Jung Liu, Wei-Xin Gao, Jhih-Yuan Chen, Chun-Han Chen, Zong-Sian Wu, Chau-Chung Hou, I-Ming Lai, Fu-Shou Tsai
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Patent number: 11681843Abstract: Various aspects of the disclosed technology relate to machine learning-based chain diagnosis. Faults are injected into scan chains in a circuit design. Simulations are performed on the fault-injected circuit design to determine test response patterns in response to the test patterns which are captured by the scan chains. Observed failing bit patterns are determined by comparing the unloaded test response patterns with corresponding good-machine test response patterns. Bit-reduction is performed on the observed failing bit patterns to construct training samples. Using the training samples, machine-learning models for faulty scan cell identification are trained. The bit reduction comprises pattern-based bit compression for good scan chains or cycle-based bit compression for the good scan chains. The bit reduction may further comprise bit-filtering. The bit-filtering may comprises keeping only sensitive bits on faulty scan chains for the training samples construction.Type: GrantFiled: January 16, 2019Date of Patent: June 20, 2023Assignee: Siemens Industry Software Inc.Inventors: Yu Huang, Gaurav Veda, Kun-Han Tsai, Wu-Tung Cheng, Mason Chern, Shi-Yu Huang
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Patent number: 11361248Abstract: Various aspects of the disclosed technology relate to machine learning-based chain diagnosis. Faults are injected into scan chains in a circuit design. Simulations are performed on the fault-injected circuit design to determine observed failing bit patterns. Bit-reduction is performed on the observed failing bit patterns to construct first training samples. Using the first training samples, first-level machine-learning models are trained. Affine scan cell groups are identified. Second training samples are prepared for each of the affine scan cell groups by performing bit-filtering on a subset of the observed failing bit patterns associated with the faults being injected at scan cells in the each of the affine scan cell groups. Using the second training samples, second-level machine-learning models are trained. The first-level and second-level machine learning models can be applied in a multi-stage machine learning-based chain diagnosis process.Type: GrantFiled: January 16, 2019Date of Patent: June 14, 2022Assignee: Siemens Industry Software Inc.Inventors: Yu Huang, Gaurav Veda, Kun-Han Tsai, Wu-Tung Cheng, Mason Chern, Shi-Yu Huang
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Patent number: 10977400Abstract: Systems and methods for a deterministic automatic test generation (ATPG) process including Timing Exception ATPG (TEA). A method includes performing an automated test pattern generation (ATPG) process that uses timing exception information to generate a test pattern for a targeted fault of a circuit design with at least one timing exception path. The method includes testing the targeted fault of the circuit design using the test pattern to produce a test result for the targeted fault.Type: GrantFiled: August 22, 2019Date of Patent: April 13, 2021Assignee: Mentor Graphics CorporationInventors: Wu-Tung Cheng, Kun-Han Tsai, Naixing Wang, Chen Wang, Xijiang Lin, Mark A. Kassab, Irith Pomeranz
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Publication number: 20200410065Abstract: Systems and methods for a deterministic automatic test generation (ATPG) process including Timing Exception ATPG (TEA). A method includes performing an automated test pattern generation (ATPG) process that uses timing exception information to generate a test pattern for a targeted fault of a circuit design with at least one timing exception path. The method includes testing the targeted fault of the circuit design using the test pattern to produce a test result for the targeted fault.Type: ApplicationFiled: August 22, 2019Publication date: December 31, 2020Inventors: Wu-Tung Cheng, Kun-Han Tsai, Naixing Wang, Chen Wang, Xijiang Lin, Mark A. Kassab, Irith Pomeranz
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Patent number: 10509073Abstract: Disclosed herein are exemplary methods, apparatus, and systems for performing timing-aware automatic test pattern generation (ATPG) that can be used, for example, to improve the quality of a test set generated for detecting delay defects or holding time defects. In certain embodiments, timing information derived from various sources (e.g. from Standard Delay Format (SDF) files) is integrated into an ATPG tool. The timing information can be used to guide the test generator to detect the faults through certain paths (e.g., paths having a selected length, or range of lengths, such as the longest or shortest paths). To avoid propagating the faults through similar paths repeatedly, a weighted random method can be used to improve the path coverage during test generation. Experimental results show that significant test quality improvement can be achieved when applying embodiments of timing-aware ATPG to industrial designs.Type: GrantFiled: July 31, 2017Date of Patent: December 17, 2019Assignee: Mentor Graphics CorporationInventors: Xijiang Lin, Kun-Han Tsai, Mark Kassab, Chen Wang, Janusz Rajski
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Publication number: 20190220776Abstract: Various aspects of the disclosed technology relate to machine learning-based chain diagnosis. Faults are injected into scan chains in a circuit design. Simulations are performed on the fault-injected circuit design to determine observed failing bit patterns. Bit-reduction is performed on the observed failing bit patterns to construct first training samples. Using the first training samples, first-level machine-learning models are trained. Affine scan cell groups are identified. Second training samples are prepared for each of the affine scan cell groups by performing bit-filtering on a subset of the observed failing bit patterns associated with the faults being injected at scan cells in the each of the affine scan cell groups. Using the second training samples, second-level machine-learning models are trained. The first-level and second-level machine learning models can be applied in a multi-stage machine learning-based chain diagnosis process.Type: ApplicationFiled: January 16, 2019Publication date: July 18, 2019Inventors: Yu Huang, Gaurav Veda, Kun-Han Tsai, Wu-Tung Cheng, Mason Chern, Shi-Yu Huang
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Publication number: 20190220745Abstract: Various aspects of the disclosed technology relate to machine learning-based chain diagnosis. Faults are injected into scan chains in a circuit design. Simulations are performed on the fault-injected circuit design to determine test response patterns in response to the test patterns which are captured by the scan chains. Observed failing bit patterns are determined by comparing the unloaded test response patterns with corresponding good-machine test response patterns. Bit-reduction is performed on the observed failing bit patterns to construct training samples. Using the training samples, machine-learning models for faulty scan cell identification are trained. The bit reduction comprises pattern-based bit compression for good scan chains or cycle-based bit compression for the good scan chains. The bit reduction may further comprise bit-filtering. The bit-filtering may comprises keeping only sensitive bits on faulty scan chains for the training samples construction.Type: ApplicationFiled: January 16, 2019Publication date: July 18, 2019Inventors: Yu Huang, Gaurav Veda, Kun-Han Tsai, Wu-Tung Cheng, Mason Chern, Shi-Yu Huang
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Patent number: 10317462Abstract: An integrated circuit for on-chip speed grading comprises test circuitry comprising scan chains and a test controller; and wide-range clock signal generation circuitry comprising phase-locked loop circuitry and frequency divider circuitry. The wide-range clock signal generation circuitry is configured to generate a wide-range test clock signal for the test circuitry to conduct a structural delay test for on-chip speed grading. The wide-range test clock signal is generated based on a test clock signal associated with the test circuitry, a frequency range selection signal and a frequency setting signal.Type: GrantFiled: May 11, 2017Date of Patent: June 11, 2019Assignee: Mentor Graphics CorporationInventors: Shi-Yu Huang, Kun-Han Tsai, Wu-Tung Cheng, Tzu-Heng Huang
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Publication number: 20180045780Abstract: Disclosed herein are exemplary methods, apparatus, and systems for performing timing-aware automatic test pattern generation (ATPG) that can be used, for example, to improve the quality of a test set generated for detecting delay defects or holding time defects. In certain embodiments, timing information derived from various sources (e.g. from Standard Delay Format (SDF) files) is integrated into an ATPG tool. The timing information can be used to guide the test generator to detect the faults through certain paths (e.g., paths having a selected length, or range of lengths, such as the longest or shortest paths). To avoid propagating the faults through similar paths repeatedly, a weighted random method can be used to improve the path coverage during test generation. Experimental results show that significant test quality improvement can be achieved when applying embodiments of timing-aware ATPG to industrial designs.Type: ApplicationFiled: July 31, 2017Publication date: February 15, 2018Applicant: Mentor Graphics CorporationInventors: Xijiang Lin, Kun-Han Tsai, Mark Kassab, Chen Wang, Janusz Rajski
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Publication number: 20170328952Abstract: An integrated circuit for on-chip speed grading comprises test circuitry comprising scan chains and a test controller; and wide-range clock signal generation circuitry comprising phase-locked loop circuitry and frequency divider circuitry. The wide-range clock signal generation circuitry is configured to generate a wide-range test clock signal for the test circuitry to conduct a structural delay test for on-chip speed grading. The wide-range test clock signal is generated based on a test clock signal associated with the test circuitry, a frequency range selection signal and a frequency setting signal.Type: ApplicationFiled: May 11, 2017Publication date: November 16, 2017Inventors: Shi-Yu Huang, Kun-Han Tsai, Wu-Tung Cheng, Tzu-Heng Huang
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Patent number: 9720038Abstract: Various aspects of the disclose techniques relate to techniques of testing interconnects in stacked designs. A single-pulse signal, generated by a first circuit state element on a first die, is applied to a first end of an interconnect and captured at a second end of the interconnect using a clock port of a second circuit state element on a second die. A faulty interconnect may cause the single-pulse signal too distorted to reach the threshold voltage of the second circuit element.Type: GrantFiled: May 19, 2014Date of Patent: August 1, 2017Assignee: Mentor Graphics, A Siemens BusinessInventors: Shi-Yu Huang, Kun-Han Tsai, Wu-Tung Cheng, Jeo-Yen Lee
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Patent number: 9720040Abstract: Disclosed herein are exemplary methods, apparatus, and systems for performing timing-aware automatic test pattern generation (ATPG) that can be used, for example, to improve the quality of a test set generated for detecting delay defects or holding time defects. In certain embodiments, timing information derived from various sources (e.g. from Standard Delay Format (SDF) files) is integrated into an ATPG tool. The timing information can be used to guide the test generator to detect the faults through certain paths (e.g., paths having a selected length, or range of lengths, such as the longest or shortest paths). To avoid propagating the faults through similar paths repeatedly, a weighted random method can be used to improve the path coverage during test generation. Experimental results show that significant test quality improvement can be achieved when applying embodiments of timing-aware ATPG to industrial designs.Type: GrantFiled: July 20, 2015Date of Patent: August 1, 2017Assignee: Mentor Graphics CorporationInventors: Xijiang Lin, Kun-Han Tsai, Mark Kassab, Chen Wang, Janusz Rajski
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Publication number: 20150323600Abstract: Disclosed herein are exemplary methods, apparatus, and systems for performing timing-aware automatic test pattern generation (ATPG) that can be used, for example, to improve the quality of a test set generated for detecting delay defects or holding time defects. In certain embodiments, timing information derived from various sources (e.g. from Standard Delay Format (SDF) files) is integrated into an ATPG tool. The timing information can be used to guide the test generator to detect the faults through certain paths (e.g., paths having a selected length, or range of lengths, such as the longest or shortest paths). To avoid propagating the faults through similar paths repeatedly, a weighted random method can be used to improve the path coverage during test generation. Experimental results show that significant test quality improvement can be achieved when applying embodiments of timing-aware ATPG to industrial designs.Type: ApplicationFiled: July 20, 2015Publication date: November 12, 2015Applicant: MENTOR GRAPHICS CORPORATIONInventors: Xijiang Lin, Kun-Han Tsai, Mark Kassab, Chen Wang, Janusz Rajski
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Patent number: 9086454Abstract: Disclosed herein are exemplary methods, apparatus, and systems for performing timing-aware automatic test pattern generation (ATPG) that can be used, for example, to improve the quality of a test set generated for detecting delay defects or holding time defects. In certain embodiments, timing information derived from various sources (e.g. from Standard Delay Format (SDF) files) is integrated into an ATPG tool. The timing information can be used to guide the test generator to detect the faults through certain paths (e.g., paths having a selected length, or range of lengths, such as the longest or shortest paths). To avoid propagating the faults through similar paths repeatedly, a weighted random method can be used to improve the path coverage during test generation. Experimental results show that significant test quality improvement can be achieved when applying embodiments of timing-aware ATPG to industrial designs.Type: GrantFiled: October 14, 2013Date of Patent: July 21, 2015Assignee: Mentor Graphics CorporationInventors: Xijiang Lin, Kun-Han Tsai, Mark Kassab, Chen Wang, Janusz Rajski
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Publication number: 20140347088Abstract: Various aspects of the disclose techniques relate to techniques of testing interconnects in stacked designs. A single-pulse signal, generated by a first circuit state element on a first die, is applied to a first end of an interconnect and captured at a second end of the interconnect using a clock port of a second circuit state element on a second die. A faulty interconnect may cause the single-pulse signal too distorted to reach the threshold voltage of the second circuit element.Type: ApplicationFiled: May 19, 2014Publication date: November 27, 2014Applicant: Mentor Graphics CorporationInventors: Shi-Yu Huang, Kun-Han Tsai, Wu-Tung Cheng, Jeo-Yen Lee
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Publication number: 20140246705Abstract: Aspects of the invention relate to techniques of testing interconnects in stacked designs for leakage defects. Logic “1” or “0” is first applied to one end of an interconnect during a first pulse. Then, logic value at the one end is captured, which triggered by an edge of a second pulse. The first pulse precedes the second pulse by a time period being selected from a plurality of delay periods. The plurality of delay periods is generated by a device shared by a plurality of interconnects.Type: ApplicationFiled: March 3, 2014Publication date: September 4, 2014Applicant: Mentor Graphics CorporationInventors: Shi-Yu Huang, Kun-Han Tsai, Wu-Tung Cheng, Yu-Hsiang Lin, Li-Ren Huang
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Publication number: 20140047404Abstract: Disclosed herein are exemplary methods, apparatus, and systems for performing timing-aware automatic test pattern generation (ATPG) that can be used, for example, to improve the quality of a test set generated for detecting delay defects or holding time defects. In certain embodiments, timing information derived from various sources (e.g. from Standard Delay Format (SDF) files) is integrated into an ATPG tool. The timing information can be used to guide the test generator to detect the faults through certain paths (e.g., paths having a selected length, or range of lengths, such as the longest or shortest paths). To avoid propagating the faults through similar paths repeatedly, a weighted random method can be used to improve the path coverage during test generation. Experimental results show that significant test quality improvement can be achieved when applying embodiments of timing-aware ATPG to industrial designs.Type: ApplicationFiled: October 14, 2013Publication date: February 13, 2014Applicant: Mentor Graphics CorporationInventors: Xijiang Lin, Kun-Han Tsai, Mark Kassab, Chen Wang, Janusz Rajski
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Patent number: 8560906Abstract: Disclosed herein are exemplary methods, apparatus, and systems for performing timing-aware automatic test pattern generation (ATPG) that can be used, for example, to improve the quality of a test set generated for detecting delay defects or holding time defects. In certain embodiments, timing information derived from various sources (e.g. from Standard Delay Format (SDF) files) is integrated into an ATPG tool. The timing information can be used to guide the test generator to detect the faults through certain paths (e.g., paths having a selected length, or range of lengths, such as the longest or shortest paths). To avoid propagating the faults through similar paths repeatedly, a weighted random method can be used to improve the path coverage during test generation. Experimental results show that significant test quality improvement can be achieved when applying embodiments of timing-aware ATPG to industrial designs.Type: GrantFiled: October 31, 2011Date of Patent: October 15, 2013Assignee: Mentor Graphics CorporationInventors: Xijiang Lin, Kun-Han Tsai, Mark Kassab, Chen Wang, Janusz Rajski
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Patent number: 8527232Abstract: Methods of diagnostic test pattern generation for small delay defects are based on identification and activation of long paths passing through diagnosis suspects. The long paths are determined according to some criteria such as path delay values calculated with SDF (Standard Delay Format) timing information and the number of logic gates on a path. In some embodiments of the invention, the long paths are the longest paths passing through a diagnosis suspect and reaching a corresponding failing observation point selected from the failure log, and N longest paths are identified for each of such pairs.Type: GrantFiled: April 27, 2010Date of Patent: September 3, 2013Assignee: Mentor Graphics CorporationInventors: Ruifeng Guo, Wu-Tung Cheng, Takeo Kobayashi, Kun-Han Tsai