Patents by Inventor KUN-HSUN LIAO

KUN-HSUN LIAO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10236931
    Abstract: A dual-mode signal transceiver includes a first transmitter circuit, a second transmitter circuit, and a receiver circuit. The first transmitter circuit is configured to operate in a first mode and configured to process a first input signal according to a first oscillating signal, in order to output a first output signal. The second transmitter circuit is configured to operate in a second mode and configured to process a second input signal according to a second oscillating signal, in order to output a second output signal, wherein a frequency of the second oscillating signal is not an integral multiple of a frequency of the first oscillating signal. The receiver circuit is configured to process an external signal associated with one of the first mode and the second mode according to the first oscillating signal, in order to read data associated with the external signal.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: March 19, 2019
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Yi-Chang Shih, Yu-Che Yang, Kun-Hsun Liao
  • Publication number: 20180109281
    Abstract: A dual-mode signal transceiver includes a first transmitter circuit, a second transmitter circuit, and a receiver circuit. The first transmitter circuit is configured to operate in a first mode and configured to process a first input signal according to a first oscillating signal, in order to output a first output signal. The second transmitter circuit is configured to operate in a second mode and configured to process a second input signal according to a second oscillating signal, in order to output a second output signal, wherein a frequency of the second oscillating signal is not an integral multiple of a frequency of the first oscillating signal. The receiver circuit is configured to process an external signal associated with one of the first mode and the second mode according to the first oscillating signal, in order to read data associated with the external signal.
    Type: Application
    Filed: August 31, 2017
    Publication date: April 19, 2018
    Inventors: Yi-Chang SHIH, Yu-Che YANG, Kun-Hsun LIAO
  • Patent number: 8669795
    Abstract: The present invention discloses a noise filtering fractional-n frequency synthesizer and an operating method thereof. The noise filtering fractional-n frequency synthesizer comprises a filter, a frequency calibration loop, a phase calibration loop and a digitally controlled delay line. The filter receives a first frequency division signal and generates a filtered signal. The frequency calibration loop is coupled to the filter and generates a first control signal. The phase calibration loop is coupled to the filter and the frequency calibration loop, and generates a second control signal. The digitally controlled delay line is coupled to the phase calibration loop and receives the second control signal. Thus, quantization noise of the fractional-n frequency synthesizer can be reduced, and phase noise of the fractional-n frequency synthesizer can be improved. In addition, the system remains locked after the filter outputs the signal.
    Type: Grant
    Filed: December 27, 2012
    Date of Patent: March 11, 2014
    Assignee: National Taiwan University
    Inventors: Shen-Iuan Liu, Kun-Hsun Liao
  • Publication number: 20140028355
    Abstract: The present invention discloses a noise filtering fractional-n frequency synthesizer and an operating method thereof. The noise filtering fractional-n frequency synthesizer comprises a filter, a frequency calibration loop, a phase calibration loop and a digitally controlled delay line. The filter receives a first frequency division signal and generates a filtered signal. The frequency calibration loop is coupled to the filter and generates a first control signal. The phase calibration loop is coupled to the filter and the frequency calibration loop, and generates a second control signal. The digitally controlled delay line is coupled to the phase calibration loop and receives the second control signal. Thus, quantization noise of the fractional-n frequency synthesizer can be reduced, and phase noise of the fractional-n frequency synthesizer can be improved. In addition, the system remains locked after the filter outputs the signal.
    Type: Application
    Filed: December 27, 2012
    Publication date: January 30, 2014
    Applicant: NATIONAL TAIWAN UNIVERSITY
    Inventors: SHEN-IUAN LIU, KUN-HSUN LIAO