Abstract: A computer system based on wafer-on-wafer architecture is provided, comprising a memory device and a logic circuit layer stacked in a wafer on wafer structural configuration. The memory device comprises a memory array and a circuit driver. The memory array comprises a shared circuit path and a plurality of memory cells, wherein the shared circuit path is connected to the memory cells. The circuit driver is connected to the shared circuit path, driving the memory cells. The logic circuit layer comprises a plurality of bonding pads for signal transmission, and a latency controller, connected to the memory array through the bonding pads, adjusting the number of memory cells connecting the shared circuit path, thereby dynamically adjusting the latency characteristics of the memory array. Embodiments of the memory device and the memory control method are also provided.

Abstract: A computer system configured to overcome the conventional bottleneck of memory throughput. A wafer-on-wafer (WOW) technology is adapted to overcome the physical limitation of quantity and length in circuit deployments. The memory devices and the memory controllers in the logic circuit layer are improved to transmit data in differential signals. The differential signals can significantly reduce the error rate in high-speed transmissions, at a voltage level far lower than that of the conventional single-end signals. Thus, the power consumption of the computer system is significantly reduced. Furthermore, the memory controller in the computer system is improved to be an integrated controller having control over physical layer signals. Thereby, the conventional physical layer interface is no longer needed in the computer system, and therefore the cost to the computer system is further reduced.

Abstract: A selectable-repairing micro light emitting diode display is provided. A backplane includes a plurality of transistor units. A plurality of pixel units are disposed on the backplane, and each of the pixel units includes a plurality of original sub-pixel units and at least one selectable-repairing sub-pixel unit. Each of the original sub-pixel units includes a set of original pad. The set of original pad is disposed on the backplane and connected to one of the transistor units. The at least one selectable-repairing sub-pixel unit is arranged between two of the original sub-pixel units next to each other and having different colors, and includes a set of repairing pad. The set of repairing pad is not connected to the transistor units. A plurality of micro light emitting elements are electrically connected to the sets of original pad and controlled to emit light through the corresponding transistor units, respectively.

Abstract: A selectable-repairing micro light emitting diode display is provided. A backplane includes a plurality of transistor units. A plurality of pixel units are disposed on the backplane, and each of the pixel units includes a plurality of original sub-pixel units and at least one selectable-repairing sub-pixel unit. Each of the original sub-pixel units includes a set of original pad. The set of original pad is disposed on the backplane and connected to one of the transistor units. The at least one selectable-repairing sub-pixel unit is arranged between two of the original sub-pixel units next to each other and having different colors, and includes a set of repairing pad. The set of repairing pad is not connected to the transistor units. A plurality of micro light emitting elements are electrically connected to the sets of original pad and controlled to emit light through the corresponding transistor units, respectively.

Abstract: A selectable-repairing micro light emitting diode display is provided. A backplane includes a plurality of transistor units. A plurality of pixel units are disposed on the backplane, and each of the pixel units includes a plurality of original sub-pixel units and at least one selectable-repairing sub-pixel unit. Each of the original sub-pixel units includes a set of original pad. The set of original pad is disposed on the backplane and connected to one of the transistor units. The at least one selectable-repairing sub-pixel unit is arranged between two of the original sub-pixel units next to each other and having different colors, and includes a set of repairing pad. The set of repairing pad is not connected to the transistor units. A plurality of micro light emitting elements are electrically connected to the sets of original pad and controlled to emit light through the corresponding transistor units, respectively.

Abstract: A control circuit for a low-temperature poly-silicon array controls the low-temperature poly-silicon array including M rows×N columns of pixel units. The control circuit includes N operational amplifiers, a comparison unit, and a pixel input switch control unit. The comparison unit determines pixel values of N red subpixels, N green subpixels, and N blue subpixels in at least one row of pixel units of the M rows of pixel units are the same as each other. The pixel input switch control unit controls, when the pixel values of the N red subpixels, the N green subpixels, and the N blue subpixels in the at least one row of pixel units of the M rows of pixel units are the same as each other, the N red pixel input switches, the N green pixel input switches, and the N blue pixel input switches to be all turned on.

Abstract: A micro light emitting diode (micro LED) display and a controller thereof are provided. The micro LED display includes a circuit board, a plurality of micro LED devices, and the controller. The micro LED devices are disposed on a first surface of the circuit board. The micro LED devices respectively have a plurality of pixel arrays. The controller is carried by the circuit board and is configured to transmit a plurality of control signals to respectively control display statuses of the pixel arrays of the micro LED devices.

Abstract: A computer system based on wafer-on-wafer architecture is provided, comprising a memory device and a logic circuit layer stacked in a wafer on wafer structural configuration. The memory device comprises a memory array and a circuit driver. The memory array comprises a shared circuit path and a plurality of memory cells, wherein the shared circuit path is connected to the memory cells. The circuit driver is connected to the shared circuit path, driving the memory cells. The logic circuit layer comprises a plurality of bounding pads for signal transmission, and a latency controller, connected to the memory array through the bounding pads, adjusting the number of memory cells connecting the shared circuit path, thereby dynamically adjusting the latency characteristics of the memory array. Embodiments of the memory device and the memory control method are also provided.

Abstract: A computer system configured to overcome the conventional bottleneck of memory throughput. A wafer-on-wafer (WOW) technology is adapted to overcome the physical limitation of quantity and length in circuit deployments. The memory devices and the memory controllers in the logic circuit layer are improved to transmit data in differential signals. The differential signals can significantly reduce the error rate in high-speed transmissions, at a voltage level far lower than that of the conventional single-end signals. Thus, the power consumption of the computer system is significantly reduced. Furthermore, the memory controller in the computer system is improved to be an integrated controller having control over physical layer signals. Thereby, the conventional physical layer interface is no longer needed in the computer system, and therefore the cost to the computer system is further reduced.

Abstract: A control circuit for a low-temperature poly-silicon array controls the low-temperature poly-silicon array including M rows×N columns of pixel units. The control circuit includes N operational amplifiers, a comparison unit, and a pixel input switch control unit. The comparison unit determines pixel values of N red subpixels, N green subpixels, and N blue subpixels in at least one row of pixel units of the M rows of pixel units are the same as each other. The pixel input switch control unit controls, when the pixel values of the N red subpixels, the N green subpixels, and the N blue subpixels in the at least one row of pixel units of the M rows of pixel units are the same as each other, the N red pixel input switches, the N green pixel input switches, and the N blue pixel input switches to be all turned on.

Abstract: A data processing method and circuit based on convolution computation are provided. In the data processing method, a shared memory structure is provided, convolution computation of data in batches or duplicated data is provided, an allocation mechanism for storing data into multiple memories is provided, and a signed padding mechanism is provided. Therefore, a flexible and efficient convolution computation mechanism and structure are provided.

Abstract: A data processing method and circuit based on convolution computation are provided. In the data processing method, a shared memory structure is provided, convolution computation of data in batches or duplicated data is provided, an allocation mechanism for storing data into multiple memories is provided, and a signed padding mechanism is provided. Therefore, a flexible and efficient convolution computation mechanism and structure are provided.

Abstract: A data processing method and circuit based on convolution computation are provided. In the data processing method, a shared memory structure is provided, convolution computation of data in batches or duplicated data is provided, an allocation mechanism for storing data into multiple memories is provided, and a signed padding mechanism is provided. Therefore, a flexible and efficient convolution computation mechanism and structure are provided.

Abstract: A selectable-repairing micro light emitting diode display is provided. A backplane includes a plurality of transistor units. A plurality of pixel units are disposed on the backplane, and each of the pixel units includes a plurality of original sub-pixel units and at least one selectable-repairing sub-pixel unit. Each of the original sub-pixel units includes a set of original pad. The set of original pad is disposed on the backplane and connected to one of the transistor units. The at least one selectable-repairing sub-pixel unit is arranged between two of the original sub-pixel units next to each other and having different colors, and includes a set of repairing pad. The set of repairing pad is not connected to the transistor units. A plurality of micro light emitting elements are electrically connected to the sets of original pad and controlled to emit light through the corresponding transistor units, respectively.

Abstract: A micro light emitting diode (micro LED) display and a controller thereof are provided. The micro LED display includes a circuit board, a plurality of micro LED devices, and the controller. The micro LED devices are disposed on a first surface of the circuit board. The micro LED devices respectively have a plurality of pixel arrays. The controller is carried by the circuit board and is configured to transmit a plurality of control signals to respectively control display statuses of the pixel arrays of the micro LED devices.

Abstract: A start-and-stop detecting apparatus for an I3C bus is provided. The start-and-stop detecting apparatus is connected with a serial data line and a serial clock line. The start-and-stop detecting apparatus includes a first start detecting circuit, a second start detecting circuit and a first OR gate. The first start detecting circuit receives a data signal, a clock signal and a reset signal, and generates a first control signal and a first output signal. The second start detecting circuit receives the data signal, the clock signal, the reset signal and the first control signal, and generates a second output signal. A first input terminal of the first OR gate receives the first output signal. A second input terminal of the first OR gate receives the second output signal. An output terminal of the first OR gate generates a start signal.

Abstract: A start-and-stop detecting apparatus for an I3C bus is provided. The start-and-stop detecting apparatus is connected with a serial data line and a serial clock line. The start-and-stop detecting apparatus includes a first start detecting circuit, a second start detecting circuit and a first OR gate. The first start detecting circuit receives a data signal, a clock signal and a reset signal, and generates a first control signal and a first output signal. The second start detecting circuit receives the data signal, the clock signal, the reset signal and the first control signal, and generates a second output signal. A first input terminal of the first OR gate receives the first output signal. A second input terminal of the first OR gate receives the second output signal. An output terminal of the first OR gate generates a start signal.

Abstract: An optical compensation method of a display panel, wherein the method includes providing an external assembly and a cloud server; obtaining a brightness image of a panel to be corrected by the external assembly; transmitting the brightness image stored in the external assembly and a serial number corresponding to the panel to be corrected to the cloud server, and recording the brightness image and the serial number as marked data; and performing an algorithm via the cloud server to generate a brightness-compensation data of the panel to be corrected based on the marked data, and storing the brightness-compensation data.

Abstract: A housing of plastic strongly bonded to a metal frame is integrally formed as the housing of an electronic device. The metal frame includes at least one plastic grabbing recess to receive portion of a plastic member, an opening of the plastic grabbing recess carries convex teeth, the convex teeth narrow the opening of the plastic grabbing recess, and the convex teeth lock portions of the plastic member.

Abstract: A housing of plastic strongly bonded to a metal frame is integrally formed as the housing of an electronic device. The metal frame includes at least one plastic grabbing recess to receive portion of a plastic member, an opening of the plastic grabbing recess carries convex teeth, the convex teeth narrow the opening of the plastic grabbing recess, and the convex teeth lock portions of the plastic member.