Abstract: A data processing method and circuit based on convolution computation are provided. In the data processing method, a shared memory structure is provided, convolution computation of data in batches or duplicated data is provided, an allocation mechanism for storing data into multiple memories is provided, and a signed padding mechanism is provided. Therefore, a flexible and efficient convolution computation mechanism and structure are provided.

Abstract: A data processing method and circuit based on convolution computation are provided. In the data processing method, a shared memory structure is provided, convolution computation of data in batches or duplicated data is provided, an allocation mechanism for storing data into multiple memories is provided, and a signed padding mechanism is provided. Therefore, a flexible and efficient convolution computation mechanism and structure are provided.

Abstract: A data processing method and circuit based on convolution computation are provided. In the data processing method, a shared memory structure is provided, convolution computation of data in batches or duplicated data is provided, an allocation mechanism for storing data into multiple memories is provided, and a signed padding mechanism is provided. Therefore, a flexible and efficient convolution computation mechanism and structure are provided.

Abstract: A start-and-stop detecting apparatus for an I3C bus is provided. The start-and-stop detecting apparatus is connected with a serial data line and a serial clock line. The start-and-stop detecting apparatus includes a first start detecting circuit, a second start detecting circuit and a first OR gate. The first start detecting circuit receives a data signal, a clock signal and a reset signal, and generates a first control signal and a first output signal. The second start detecting circuit receives the data signal, the clock signal, the reset signal and the first control signal, and generates a second output signal. A first input terminal of the first OR gate receives the first output signal. A second input terminal of the first OR gate receives the second output signal. An output terminal of the first OR gate generates a start signal.

Abstract: A start-and-stop detecting apparatus for an I3C bus is provided. The start-and-stop detecting apparatus is connected with a serial data line and a serial clock line. The start-and-stop detecting apparatus includes a first start detecting circuit, a second start detecting circuit and a first OR gate. The first start detecting circuit receives a data signal, a clock signal and a reset signal, and generates a first control signal and a first output signal. The second start detecting circuit receives the data signal, the clock signal, the reset signal and the first control signal, and generates a second output signal. A first input terminal of the first OR gate receives the first output signal. A second input terminal of the first OR gate receives the second output signal. An output terminal of the first OR gate generates a start signal.

Abstract: A method for accessing a multi-port memory module comprising a plurality of banks is provided, wherein the plurality of banks comprise at least a first bank, a second bank and a reference bank, and the method comprises: when first data is requested to be written into the first bank, reading reference data from the reference bank, and encoding the first data with the reference data to generate first encoded data, and writing the first encoded data into the first bank; and when second data is requested to be written into the second bank, reading the same reference data from the reference bank, and encoding the second data with the reference data to generate second encoded data, and writing the second encoded data into the second bank.