Abstract: A method is disclosed for forming a low resistance poly landing pad which is achieved by shunting the polysilicon of a landing pad with metallic conductors. A window is opened through a first dielectric layer to expose a conducting region over a semiconductor substrate. A metallic layer, deposited overall, is followed by an overall deposition of a polysilicon layer, with the layers being sufficient to fill the window completely. Metal and polysilicon outside the window is removed by chemical/mechanical polishing which also provides global planarization. Salicidation provides a silicide cover over the exposed surface of polysilicon, which was formed by the polishing. A second dielectric is deposited and an opening is formed to the landing pad.

Abstract: A method of fabricating a metal contact in a reduced aspect ratio contact hole. The method begins by forming a first insulating layer and a first barrier layer having a first barrier opening over a substrate. The first insulating layer is anisotropically etched through the first barrier opening forming an upper contact hole. A second barrier layer is formed on the first barrier layer and the first insulating layer. The second barrier layer is anisotropically etched forming spacers on sidewalls of the first insulating layer. The first insulating layer is anisotropically etched using the first barrier layer and the spacers as an etch mask forming a lower contact hole. The first barrier layer and the spacers are removed to form the reduced aspect ratio contact hole. The reduced aspect ratio contact hole is comprised by the upper and lower contact holes. The reduced aspect ratio contact hole is filled with a contact metal to contact the contact region in the substrate.

Abstract: A new method of forming a tunneling oxide film having a uniform thickness in the fabrication of a Flash EEPROM memory cell is described. A first oxide layer is provided on the surface of a semiconductor substrate wherein a portion of the first oxide layer is removed to expose the semiconductor substrate wherein the exposed portion of the semiconductor substrate comprises a tunneling window. A second oxide layer is deposited within the tunneling window. Thereafter, a thermal oxide layer is grown underlying the first oxide layer and the second oxide layer within the tunneling area wherein the presence of the second oxide layer provides for a uniform thermal oxide thickness throughout the tunneling window and wherein the second oxide layer and the thermal oxide layer together within the tunneling window form the tunneling oxide film in the fabrication of a memory cell.