Patents by Inventor Kun-Lin Wu

Kun-Lin Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6140232
    Abstract: A method for forming narrow line width silicide having reduced sheet resistance is disclosed by the present invention. The method includes: firstly, providing a semiconductor substrate, whereon there formed at least a source/drain region and a gate region, as well as a spacer formed on a sidewall of the gate region; then, depositing a titanium metal layer overlying the semiconductor substrate and the resulting structure; next, carrying out rapid thermal processing and RCA cleaning to form a first titanium silicide layer; consequentially, forming a selective polysilicon layer over the first titanium silicide layer; and, depositing a second titanium metal layer over the selective polysilicon layer and overlying the exposed surface of spacer; finally, carrying out rapid thermal processing and RCA cleaning once again to form a second titanium silicide layer. The overall thickness of titanium silicide is depending on the requiring resistance of titanium silicide under a certain line width.
    Type: Grant
    Filed: August 31, 1999
    Date of Patent: October 31, 2000
    Assignee: United Microelectronics Corp.
    Inventors: Yu-Tsai Lin, Kun-Lin Wu
  • Patent number: 6119294
    Abstract: An auto brush pressure cleaning system is described. The system includes a first pneumatic brush, a second pneumatic brush disposed to align with the first pneumatic brush adjacent and parallel to the first pneumatic brush, and a computer. The system also includes a first brush pressure regulator electrically coupled to the computer and transmitting a first and a second signal to the computer and a second brush pressure regulator coupled to the second pneumatic brush and the first brush pressure regulator through a first three-way valve and electrically coupled to the computer, wherein the second pneumatic brush transmits a third signal to the second brush pressure regulator and to the first brush pressure regulator and the second brush pressure regulator transmits a fourth signal to the computer.
    Type: Grant
    Filed: January 14, 1999
    Date of Patent: September 19, 2000
    Assignee: United Microelectronics Corp.
    Inventors: Chien-Hsin Lai, Juen-Kuen Lin, Kun-Lin Wu, Peng-Yih Peng
  • Patent number: 6120366
    Abstract: The invention provides a chemical-mechanical polishing pad, which includes a plurality of annular grooves and a plurality of streamline grooves designed according to principles of the hydrodynamics. The streamline grooves of polishing pad are designed according to flow equations derived from source flow and vortex flow, and the streamline grooves of polishing pad uniformly distribute the slurry on the polishing pad. An angle and a depth of the streamline groove, which are calculated by boundary layer effect of the streamline groove function, are used to design an optimum structure for polishing pad.
    Type: Grant
    Filed: January 4, 1999
    Date of Patent: September 19, 2000
    Assignee: United Microelectronics Corp.
    Inventors: Juen-Kuen Lin, Chien-Hsin Lai, Peng-Yih Peng, Edward Yang, Kun-Lin Wu, Fu-Yang Yu
  • Patent number: 6077784
    Abstract: A chemical-mechanical polishing process for forming a metallic interconnect includes the steps of providing a semiconductor substrate having a first metallic line thereon, and then forming a dielectric layer over the substrate and the first metallic line. Next, a chemical-mechanical polishing method is used to polish the surface of the dielectric layer. Thereafter, a thin cap layer is formed over the polished dielectric layer. The thin cap layer having a thickness of between 1000-3000 .ANG. can be, for example, a silicon dioxide layer, a phosphosilicate glass layer or a silicon-rich oxide layer. The method of forming the cap layer includes depositing silicon oxide using a chemical vapor deposition method with silicane (SiH.sub.4) or tetra-ethyl-ortho-silicate (TEOS) as the main reactive agent. Alternatively, the cap layer can be formed by depositing silicon nitride using a chemical vapor deposition method with silicane or silicon dichlorohydride (SiH.sub.2 Cl.sub.2) as the main reactive agent.
    Type: Grant
    Filed: August 11, 1998
    Date of Patent: June 20, 2000
    Assignee: United Microelectronics Corp.
    Inventors: Kun-Lin Wu, Meng-Jin Tsai
  • Patent number: 6071806
    Abstract: A method for preventing the occurrence of poisoned trenches and vias in a dual damascene process that includes performing a densification process, such as an electron-beam process, on the surface of the exposed dielectric layer around the openings before the openings are filled with conductive material. The densified surface of the dielectric layer is able to efficiently prevent the occurrence of poisoned trenches and vias caused by the outgassing phenomena.
    Type: Grant
    Filed: September 14, 1998
    Date of Patent: June 6, 2000
    Assignee: United Microelectronics Corp.
    Inventors: Kun-Lin Wu, Horng-Bor Lu
  • Patent number: 6062963
    Abstract: A chemical-mechanical polishing machine having an improved wafer retainer ring design for the polishing head, comprising a polishing table, a polishing pad, a polishing head and a wafer retainer ring, wherein the polishing pad is above the polishing table, the polishing head is above the polishing pad, and the wafer retainer ring is mounted onto the polishing head. Improvement of the retainer ring design includes the formation of a plurality of guiding holes around the periphery of the retainer ring such that the guiding hole axis follows the centrifugal line produced by a rotating polishing head. Furthermore, the guiding hole has a gradual diffusing structure from the outer inlet to the inner outlet.
    Type: Grant
    Filed: April 14, 1998
    Date of Patent: May 16, 2000
    Assignee: United Microelectronics Corp.
    Inventors: Juen-Kuen Lin, Chien-Hsin Lai, Peng-Yih Peng, Hao-Kuang Chiu, Kun-Lin Wu
  • Patent number: 6057248
    Abstract: A method of removing residual contaminants in grooves of an alignment mark of a semiconductor wafer after a chemical-mechanical polishing is disclosed. The method includes scrubbing the semiconductor wafer using conventional scrubbing technique. Next, the semiconductor wafer is etched back to remove a damaged layer, which is formed during the chemical-mechanical polishing, over the semiconductor wafer. Finally, the semiconductor wafer is cleaned, for example, by NH.sub.4 OH/H.sub.2 O.sub.2 /DI, agitated by a megasonic source, thereby substantially removing the residual contaminants from the alignment mark.
    Type: Grant
    Filed: July 21, 1997
    Date of Patent: May 2, 2000
    Assignee: United Microelectronics Corp.
    Inventors: Kun-Lin Wu, Horng-Bor Lu
  • Patent number: 6030892
    Abstract: A method of preventing overpolishing in a chemical-mechanical polishing operation includes using a spin-on polymer material instead of spin-on glass as the local planarization material. The spin-on polymer layer is further used as a polishing stop layer so as to prevent damage to components due to overpolishing, because the polishing rate of the spin-on polymer layer in a chemical-mechanical polishing operation is, in general, lower than the polishing rate of the silicon dioxide layer formed using plasma enhanced chemical vapor deposition.
    Type: Grant
    Filed: May 30, 1997
    Date of Patent: February 29, 2000
    Assignee: United Microelectronics Corp.
    Inventors: Kun-Lin Wu, Hao-Kuang Chiu, Horng-Bor Lu, Jenn-Tarng Lin
  • Patent number: 6013581
    Abstract: A method for preventing the occurrence of poisoned trenches and vias in a dual damascene process that includes performing a densification process, such as an plasma treatment, on the surface of the exposed dielectric layer around the openings before the openings are filled with conductive material. The densified surface of the dielectric layer is able to efficiently prevent the occurrence of poisoned trenches and vias caused by the outgassing phenomena.
    Type: Grant
    Filed: October 5, 1998
    Date of Patent: January 11, 2000
    Assignee: United Microelectronics Corp.
    Inventors: Kun-Lin Wu, Horng-Bor Lu
  • Patent number: 6013559
    Abstract: A method of fabricating a trench isolation structure in a semiconductor devices. First, a mask layer is formed on a substrate and patterned. Then, a trench is formed in the substrate using the mask layer as a mask. An insulating layer is formed under the mask layer to fill the trench. The insulating layer is polished to expose a portion of the mask layer and an insulating plug is left in the trench. A RTP is performed to avoid mobile ions diffuse into the substrate. There are several operating conditions for the RTP. For example the operating temperature is ranged from about 600.degree. C. to about 1300.degree. C. The duration for performing the RTP is ranged from about 5 seconds to about 5 minutes. The operating gas can be selected from one of a group of N.sub.2, O.sub.2, or N.sub.2 O. Besides, before the RTP a cleaning step is performed using SC-1 or hydrogen fluoride (HF) solution as cleaning solution.
    Type: Grant
    Filed: October 14, 1998
    Date of Patent: January 11, 2000
    Assignee: United Microelectronics Corp.
    Inventors: Kun-Lin Wu, Horng-Bor Lu
  • Patent number: 5883004
    Abstract: A method for planarizing interlayer dielectric is disclosed. The present invention includes firstly forming a barrier layer over a semiconductor substrate. Next, a buffer layer is formed on the barrier layer by a spin-on-glass technique. A dielectric layer is formed on the buffer layer, wherein etch rate of the dielectric layer is larger than etch rate of the buffer layer, and the barrier layer serves as a block of autodoping coming from the dielectric layer. Finally, the dielectric layer is etched back using the buffer layer as buffer, thereby planarizing the dielectric layer.
    Type: Grant
    Filed: August 25, 1997
    Date of Patent: March 16, 1999
    Assignee: United Microelectronics Corp.
    Inventors: Hao-Kuang Shiu, Kun-Lin Wu, Horng-Bor Lu, Jenn-Tarng Lin
  • Patent number: 5876508
    Abstract: A method for effectively cleaning the slurry remnants left on a polishing pad after the completion of a chemical mechanical polish (CMP) process is provided. This method is able to substantially thoroughly clean away all of the slurry remnants left on the polishing pad. In the method of the invention, the first step is to prepare a cleaning agent which is a mixture of H.sub.2 O.sub.2, deionized water, an acid solution, and an alkaline solution mixed to a predetermined ratio. The cleaning agent is subsequently directed to a nozzle formed in the pad dresser. This allows the cleaning agent to be jetted forcibly onto the slurry remnants on the polishing pad so as to clean the slurry remnants away from the polishing pad. The cleaning agent can be provided with predetermined ratios for various kinds of slurries so that the cleaning agent can be adjusted to be either acid or alkaline in nature.
    Type: Grant
    Filed: March 17, 1997
    Date of Patent: March 2, 1999
    Assignee: United Microelectronics Corporation
    Inventors: Kun-Lin Wu, Chien-Hsien Lai, Horng-Bor Lu, Jenn-Tarng Lin