Abstract: An IC package architecture and a method of manufacturing the same are provided. By this packaging method, a molded compound is first formed, which covers the entire packaging area of the leadframe but leaving a window to expose the area where the chip is to be mounted. After the chip is mounted and wire bonded, a dispensed compound is formed the window to enclose the chip therein. The dispensing material can be variably selected by the manufacturer in accordance with actual application requirements. For instance, the dispensing material can be either a transparent material to allow the enclosed chip to be transparent to the outside, or a colored material for some prespecified identification purpose of the IC package. Moreover, the packaging method can be utilized on current types of IC packages and can be realized by using existing equipment and processes in a cost-effective manner without having to invest on new additional ones.

Abstract: An architecture for a dual-chip IC package and a method of manufacturing the same are provided. The dual-chip IC package allows two chips to be mounted on the same leadframe in the same package. The two chips can be either the same type of a semiconductor device or two different types of semiconductor devices with different functions such as a memory chip and a logic control chip. The architecture allows a simplified manufacturing process and an increased good yield rate for the two IC chips that are to be enclosed in the dual-chip IC package. Moreover, the dual-chip IC package can be manufactured with existing packaging equipment and processes, so that it can be realized without having to invest on and install additional ones.

Abstract: A data sensing apparatus particularly useful for sensing a ROM device. The apparatus can be used with various voltage level devices because it has an adjustable load. A first load element is connected to the voltage source applied to the ROM device. A second load element is connected in parallel with the first load element. A switching element is connected to the first load element and provides a path for a sensing current of the ROM device. An inverter, responsive to the sensing current, controls the switching element. An amplifier, connected to the switching element, provides a useful output indicative of the sensing current of the ROM device. A voltage level detector detects the voltage level of the voltage source. It disables the second load element so as to increase the load when the voltage level of the voltage source is higher than a predetermined value.

Abstract: A process of fabricating a semiconductor device on a substrate with closely spaced high density conductive lines is provided. A thin insulating layer is formed on the surface of a substrate. Next, a blanket conductive layer and a blanket masking layer are deposited over the first insulating layer. Using conventional photolithography processes and plasma etching, elongated spaced parallel masking lines with vertical sidewalls are formed in the masking layer. A blanket polycrystalline silicon layer is deposited on the masking lines and the exposed areas of the conductive layer. Next, the blanket polycrystalline silicon layer is anisotrophically etched to form spacers on the vertical sidewalls of the masking lines. A second planarized masking layer is formed over the spacers and masking lines. The polycrystalline silicon spacers and the underlying first polycrystalline silicon layer are anisotrophically etched to form the closely spaced conductive lines in the first polycrystalline silicon layer.

Abstract: A process of fabricating a non-volatile read only memory device (ROM) wherein the conductive word lines have desirable very narrow widths and are closely spaced. The invention provides a process for forming word lines with a smaller width and line pitch than is possible with conventional processes. A first set of word lines is formed. Next, a second set of word lines is formed in between the first word lines using oxide spacers to define the second word lines.

Abstract: A new method of forming a self-aligning polysilicon gate is described. A gate silicon oxide is formed over a silicon substrate. A polysilicon layer is formed over the gate oxide. A native silicon oxide layer is formed over the polysilicon layer. A second polysilicon layer is formed over the native silicon oxide layer. Additional alternating layers of polysilicon and native silicon oxide are formed as desired. The wafer is annealed at between about 800.degree. to 1000.degree. C. This causes, it is believed, the silicon oxide gas from the multiple native silicon oxide layers to be exhausted resulting in the removal of all silicon oxide layers. A polycide layer is formed overlying the multiple polysilicon layers, if desired. Conventional lithography and etching techniques are used to form a gate. Ions are implanted into the substrate to form source/drain regions, using the multilayer gate as a mask. Rapid thermal annealing activates the impurities.

Abstract: A cost-effective and manufacturable method for producing ROM integrated circuits with closely-spaced self-aligned conductive lines, on the order of 0.3 micrometers apart, is described. Parallel, conductive semiconductor device structures are formed in a semiconductor substrate. An insulating layer is formed over the semiconductor substrate. A first conductive polysilicon layer is formed over the insulating layer. The first conductive polysilicon layer is patterned to form first polysilicon conductor lines which are parallel to each other, and orthogonal to the parallel, conductive semiconductor device structures. A first silicon oxide layer is formed on and between the first polysilicon conductor lines. The first silicon oxide layer is anisotropically etched to produce sidewall structures on the first polysilicon conductor lines. A second silicon oxide layer is formed on and between the first polysilicon conductor lines.