Abstract: A semiconductor biosensor diagnostic system is provided. The semiconductor biosensor diagnostic system includes a diagnostic cartridge and a cartridge diagnostic base. The diagnostic cartridge includes a biosensor device and a fluid-guide body over the biosensor device. The fluid-guide body includes a first pumping opening, a second pumping opening, a buffer reservoir, a sample reservoir, and a plurality of channels configured to provide a first loop including the first pumping opening and the buffer reservoir, and a second loop including the second pumping opening and the sample reservoir. The first loop and the second loop sharing a common channel passing through the biosensor device. The cartridge diagnostic base includes a plurality of micro pumps coupled to the first pumping opening and the second pumping opening, and a sensing structure configured to receive a sensing information from the biosensor device.

Abstract: An integrated biosensor structure is provided. The integrated biosensor structure includes a CMOS structure and a sensing oxide layer. The CMOS structure includes a substrate having a first surface, the substrate includes a sensing region and a logic region surrounding the sensing region; a FEOL structure having a plurality of doped regions at the first surface of the substrate; and a BEOL structure over the FEOL structure. The BEOL structure includes a first trench penetrating the BEOL structure. The sensing oxide layer is disposed over the BEOL structure and in contact with the sensing region of the substrate through the first trench. The sensing oxide layer is conformal with the first trench of the BEOL structure to form a sensing trench. A method of manufacturing an integrated biosensor structure is also provided.

Abstract: A system-on-chip semiconductor circuit includes a logic circuit having at least one first transistor with a thin gate dielectric, at least one dynamic random access memory cell coupled with the logic circuit having at least one storage capacitor and at least one thick gate dielectric access transistor, and an analog circuit operable with the logic circuit and the memory cell having at least one thick gate dielectric switched transistor and at least one switched capacitor, wherein the storage capacitors of the memory cell and the switched transistors are of the same type, and wherein the thick gate dielectric switched transistor and the switched capacitor of the analog circuit are made by a process for making the dynamic random access memory cell.

Abstract: A system for improving reliability of a memory device includes one or more memory banks, each of which has one or more regular memory cell rows and one or more redundant memory cell rows. At least one built-in-self-test (BIST) unit is coupled to the memory banks for testing the redundant memory cell rows to determine their respective quality standards, and testing the regular memory cell rows to identify the regular memory cell row that fails to pass a predetermined quality standard. At least one built-in-self-repair (BISR) unit is coupled to the BIST unit for replacing the failed regular memory cell row with the redundant memory cell row having a quality standard equal to or higher than the predetermined quality standard. The BIST unit repeatedly tests the regular memory cell rows a number of times, with each time applying a different quality standard.

Abstract: A system and method for writing a SRAM cell coupled to complimentary first and second bit-lines (BLs) is disclosed, the method comprising asserting a word-line (WL) selecting the SRAM cell to a first positive voltage, providing a second positive voltage at the first BL, providing a first negative voltage at the second BL, and asserting a plurality of WLs not selecting the SRAM cell to a second negative voltage, wherein the writing margin of the SRAM cell is increased.

Abstract: A system-on-chip semiconductor circuit includes a logic circuit having at least one first transistor with a thin gate dielectric, at least one dynamic random access memory cell coupled with the logic circuit having at least one storage capacitor and at least one thick gate dielectric access transistor, and an analog circuit operable with the logic circuit and the memory cell having at least one thick gate dielectric switched transistor and at least one switched capacitor, wherein the storage capacitors of the memory cell and the switched transistors are of the same type, and wherein the thick gate dielectric switched transistor and the switched capacitor of the analog circuit are made by a process for making the dynamic random access memory cell.

Abstract: A system and method for writing a SRAM cell coupled to complimentary first and second bit-lines (BLs) is disclosed, the method comprising asserting a word-line (WL) selecting the SRAM cell to a first positive voltage, providing a second positive voltage at the first BL, providing a first negative voltage at the second BL, and asserting a plurality of WLs not selecting the SRAM cell to a second negative voltage, wherein the writing margin of the SRAM cell is increased.

Abstract: A configurable logic and memory block (CLMB) and a configurable logic device are disclosed. The CLMB includes one or more static random access memory (SRAM) cells, a first output module for generating a first output by reading at least one SRAM cell when the CLMB functions as an SRAM, a second output module for generating a second output by reading at least one SRAM cell when the CLMB functions as a program logic device (PLD), wherein data on one or more bitlines coupled to the SRAM cells are controllably feeding into the first and second output modules. The configurable logic device can provide various Boolean logic functions using pass gates.

Abstract: A system for improving reliability of a memory device includes one or more memory banks, each of which has one or more regular memory cell rows and one or more redundant memory cell rows. At least one built-in-self-test (BIST) unit is coupled to the memory banks for testing the redundant memory cell rows to determine their respective quality standards, and testing the regular memory cell rows to identify the regular memory cell row that fails to pass a predetermined quality standard. At least one built-in-self-repair (BISR) unit is coupled to the BIST unit for replacing the failed regular memory cell row with the redundant memory cell row having a quality standard equal to or higher than the predetermined quality standard. The BIST unit repeatedly tests the regular memory cell rows a number of times, with each time applying a different quality standard.

Abstract: A memory cell for a static random access memory (SRAM) is disclosed that can be programmed to have a one-bit cell or a multi-bit cell (i.e, including two or more latches) according to a desired amount of cell current. For lower current needs, the memory cell can incorporate a single bit-element, while for higher current needs the memory cell can incorporate two or more bit-elements. An exemplary static random access memory device includes a memory cell having one or more bit-elements, such as bistable latches. Access devices, such as pass transistors, are coupled between each of the bit-elements and a bit line. A word line is coupled to the control terminal of each of the pass transistors for controlling communication between the bit-elements and the bit line.

Abstract: A memory cell for a static random access memory (SRAM) is disclosed that can be programmed to have a one-bit cell or a multi-bit cell (i.e., including two or more latches) according to a desired amount of cell current. For lower current needs, the memory cell can incorporate a single bit-element, while for higher current needs the memory cell can incorporate two or more bit-elements. An exemplary static random access memory device includes a memory cell having one or more bit-elements, such as bistable latches. Access devices, such as pass transistors, are coupled between each of the bit-elements and a bit line. A word line is coupled to the control terminal of each of the pass transistors for controlling communication between the bit-elements and the bit line.