Patents by Inventor Kun Lung Chen
Kun Lung Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240093416Abstract: A sewing machine includes a main body and a quick release needle plate module. The main body includes a base seat having an inner frame, and an outer case that is mounted to the inner frame and that defines an accommodating compartment. The quick release needle plate module includes a catch member, and a needle plate that covers the accommodating compartment, that is detachably pivoted to a rear section of the inner frame, and that engages the catch member. The quick release needle plate module further includes a press member inserted through the outer case and the inner frame, and operable to push the catch member to disengage the catch member. The needle plate has a plate body that covers the accommodating compartment, and a resilient member mounted between the inner frame and the plate body for driving pivot action of the plate body away from the inner frame.Type: ApplicationFiled: January 20, 2023Publication date: March 21, 2024Applicant: ZENG HSING INDUSTRIAL CO., LTD.Inventors: Kun-Lung HSU, Ming-Ta LEE, Wei-Chen CHEN, Po-Hsien TSENG
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Publication number: 20240085398Abstract: A semiconductor device includes a circuit layer and a nanopore layer. The nanopore layer is formed on the circuit layer and is formed with a pore therethrough. The circuit layer includes a circuit unit configured to drive a biomolecule through the pore and to detect a current associated with a resistance of the nanopore layer, whereby a characteristic of the biomolecule can be determined using the currents detected by the circuit unit.Type: ApplicationFiled: November 21, 2023Publication date: March 14, 2024Inventors: Kun-Lung Chen, Tung-Tsun Chen, Cheng-Hsiang Hsieh, Yu-Jie Huang, Jui-Cheng Huang
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Publication number: 20240072571Abstract: A wireless transmission module for transmitting energy or signals includes a first magnetically conductive element, a first coil assembly and a first adhesive element. The first coil assembly and the first magnetically conductive element are arranged along a main axis. The first adhesive element is configured to be adhered to the first coil assembly and the first magnetic conductive element. The first adhesive element is disposed between the first coil assembly and the first magnetically conductive element.Type: ApplicationFiled: December 16, 2022Publication date: February 29, 2024Inventors: Feng-Lung CHIEN, Mao-Chun CHEN, Kun-Ying LEE, Yuan HAN, Tsang-Feng WU
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Patent number: 11916084Abstract: A transparent display panel with driving electrode regions, circuit wiring regions, and optically transparent regions is provided. The driving electrode regions are arranged into an array in a first direction and a second direction. An average light transmittance of the circuit wiring regions is less than ten percent, and an average light transmittance of the optically transparent regions is greater than that of the driving electrode regions and the circuit wiring regions. The first direction intersects the second direction. The circuit wiring regions connect the driving electrode regions at intervals, such that each optically transparent region spans among part of the driving electrode regions. The transparent display panel includes first signal lines and second signal lines extending along the circuit wiring regions, and each circuit wiring region is provided with at least one of the first signal lines and at least one of the second signal lines.Type: GrantFiled: August 24, 2022Date of Patent: February 27, 2024Assignee: AUO CorporationInventors: Chun-Yu Lin, Kun-Cheng Tien, Jia-Long Wu, Ming-Lung Chen, Shu-Hao Huang
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Patent number: 11860152Abstract: A semiconductor device includes a circuit layer and a nanopore layer. The nanopore layer is formed on the circuit layer and is formed with a pore therethrough. The circuit layer includes a circuit unit configured to drive a biomolecule through the pore and to detect a current associated with a resistance of the nanopore layer, whereby a characteristic of the biomolecule can be determined using the currents detected by the circuit unit.Type: GrantFiled: July 8, 2020Date of Patent: January 2, 2024Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Kun-Lung Chen, Tung-Tsun Chen, Cheng-Hsiang Hsieh, Yu-Jie Huang, Jui-Cheng Huang
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Publication number: 20230384259Abstract: An on-chip heater in a concentric rings configuration having non-uniform spacing between heating elements provides improved radial temperature uniformity and low power consumption compared to circular or square heating elements. On-chip heaters are suitable for integration and use with on-chip sensors that require tight temperature control.Type: ApplicationFiled: August 10, 2023Publication date: November 30, 2023Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tung-Tsun Chen, Jui-Cheng HUANG, Kun-Lung CHEN, Cheng-Hsiang HSIEH
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Publication number: 20230280391Abstract: An apparatus and method for testing gallium nitride field effect transistors (GaN FETs) are disclosed herein. In some embodiments, the apparatus includes: a high side GaN FET, a low side GaN FET, a high side driver coupled to a gate of the high side GaN FET, a low side driver coupled to a gate of the low side GaN FET, and a driver circuit coupled to the high side and low side drivers and configured to generate drive signals capable of driving the high and low side GaN FETs, wherein the high and low side GaN FETs and transistors, within the high and low side drivers and the driver circuit, are patterned on a same semiconductor device layer during a front-end-of-line (FEOL) process.Type: ApplicationFiled: May 11, 2023Publication date: September 7, 2023Inventors: Yu-Ann LAI, Ruo-Rung HUANG, Kun-Lung CHEN, Chun-Yi YANG, Chan-Hong CHERN
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Publication number: 20230266266Abstract: An integrated biosensor structure is provided. The integrated biosensor structure includes a CMOS structure and a sensing oxide layer. The CMOS structure includes a substrate having a first surface, the substrate includes a sensing region and a logic region surrounding the sensing region; a FEOL structure having a plurality of doped regions at the first surface of the substrate; and a BEOL structure over the FEOL structure. The BEOL structure includes a first trench penetrating the BEOL structure. The sensing oxide layer is disposed over the BEOL structure and in contact with the sensing region of the substrate through the first trench. The sensing oxide layer is conformal with the first trench of the BEOL structure to form a sensing trench. A method of manufacturing an integrated biosensor structure is also provided.Type: ApplicationFiled: October 25, 2022Publication date: August 24, 2023Inventor: KUN LUNG CHEN
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Patent number: 11680978Abstract: An apparatus and method for testing gallium nitride field effect transistors (GaN FETs) are disclosed herein. In some embodiments, the apparatus includes: a high side GaN FET, a low side GaN FET, a high side driver coupled to a gate of the high side GaN FET, a low side driver coupled to a gate of the low side GaN FET, and a driver circuit coupled to the high side and low side drivers and configured to generate drive signals capable of driving the high and low side GaN FETs, wherein the high and low side GaN FETs and transistors, within the high and low side drivers and the driver circuit, are patterned on a same semiconductor device layer during a front-end-of-line (FEOL) process.Type: GrantFiled: September 30, 2020Date of Patent: June 20, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yu-Ann Lai, Ruo-Rung Huang, Kun-Lung Chen, Chun-Yi Yang, Chan-Hong Chern
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Publication number: 20230076455Abstract: Various embodiments of the present application are directed towards a level shifter with temperature compensation. In some embodiments, the level shifter comprises a transistor, a first resistor, and a second resistor. The first resistor is electrically coupled from a first source/drain of the transistor to a supply node, and the second resistor is electrically coupled from a second source/drain of the transistor to a reference node. Further, the first and second resistors have substantially the same temperature coefficients and comprise group III-V semiconductor material. By having both the first and second resistors, the output voltage of the level shifter is defined by the resistance ratio of the resistors. Further, since the first and second resistors have the same temperature coefficients, temperature induced changes in resistance is largely cancelled out in the ratio and the output voltage is less susceptible to temperature induced change than the first and second resistors individually.Type: ApplicationFiled: November 15, 2022Publication date: March 9, 2023Inventors: Chan-Hong Chern, Kun-Lung Chen
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Patent number: 11522526Abstract: Various embodiments of the present application are directed towards a level shifter with temperature compensation. In some embodiments, the level shifter comprises a transistor, a first resistor, and a second resistor. The first resistor is electrically coupled from a first source/drain of the transistor to a supply node, and the second resistor is electrically coupled from a second source/drain of the transistor to a reference node. Further, the first and second resistors have substantially the same temperature coefficients and comprise group III-V semiconductor material. By having both the first and second resistors, the output voltage of the level shifter is defined by the resistance ratio of the resistors. Further, since the first and second resistors have the same temperature coefficients, temperature induced changes in resistance is largely cancelled out in the ratio and the output voltage is less susceptible to temperature induced change than the first and second resistors individually.Type: GrantFiled: April 5, 2021Date of Patent: December 6, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chan-Hong Chern, Kun-Lung Chen
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Publication number: 20220368326Abstract: Devices, systems, and methods are provided for generating a high, dynamic voltage boost. An integrated circuit (IC) includes a driving circuit having a first stage and a second stage. The driving circuit is configured to provide an overdrive voltage. The IC also includes a charge pump circuit coupled between the first stage and the second stage. The charge pump circuit is configured generate a dynamic voltage greater than the overdrive voltage. The IC also includes a bootstrap circuit coupled to the charge pump circuit, configured to further dynamically boost the overdrive voltage of the driving circuit.Type: ApplicationFiled: July 28, 2022Publication date: November 17, 2022Inventors: Chan-Hong Chern, Tysh-Bin Liu, Kun-Lung Chen
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Publication number: 20220336295Abstract: A manufacturing method of group III-V semiconductor package is provided. The manufacturing method includes the following steps. A wafer comprising group III-V semiconductor dies therein is provided. A chip probing (CP) process is performed to the wafer to determine reliabilities of the group III-V semiconductor dies, wherein the CP process comprises performing a multi-step breakdown voltage testing process to the group III-V semiconductor dies to obtain a first portion of dies of the group III-V semiconductor dies with breakdown voltages to be smaller than a predetermined breakdown voltage. A singulation process is performed to separate the group III-V semiconductor dies from the wafer. A package process is performed to form group III-V semiconductor packages including the group III-V semiconductor dies. A final testing process is performed on the group III-V semiconductor packages.Type: ApplicationFiled: September 15, 2021Publication date: October 20, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi-An Lai, Chan-Hong Chern, Chih-Hua Wang, Chu-Fu Chen, Kun-Lung Chen
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Patent number: 11437990Abstract: Devices, systems, and methods are provided for generating a high, dynamic voltage boost. An integrated circuit (IC) includes a driving circuit having a first stage and a second stage. The driving circuit is configured to provide an overdrive voltage. The IC also includes a charge pump circuit coupled between the first stage and the second stage. The charge pump circuit is configured generate a dynamic voltage greater than the overdrive voltage. The IC also includes a bootstrap circuit coupled to the charge pump circuit, configured to further dynamically boost the overdrive voltage of the driving circuit.Type: GrantFiled: May 24, 2021Date of Patent: September 6, 2022Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Chan-Hong Chern, Tysh-Bin Liu, Kun-Lung Chen
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Patent number: 11360073Abstract: A semiconductor device includes a circuit layer and a nanopore layer. The nanopore layer is formed on the circuit layer and is formed with a pore therethrough. The circuit layer includes a circuit unit configured to drive a biomolecule through the pore and to detect a current associated with a resistance of the nanopore layer, whereby a characteristic of the biomolecule can be determined using the currents detected by the circuit unit.Type: GrantFiled: June 11, 2020Date of Patent: June 14, 2022Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Kun-Lung Chen, Tung-Tsun Chen, Cheng-Hsiang Hsieh, Yu-Jie Huang, Jui-Cheng Huang
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Publication number: 20220099726Abstract: An apparatus and method for testing gallium nitride field effect transistors (GaN FETs) are disclosed herein. In some embodiments, the apparatus includes: a high side GaN FET, a low side GaN FET, a high side driver coupled to a gate of the high side GaN FET, a low side driver coupled to a gate of the low side GaN FET, and a driver circuit coupled to the high side and low side drivers and configured to generate drive signals capable of driving the high and low side GaN FETs, wherein the high and low side GaN FETs and transistors, within the high and low side drivers and the driver circuit, are patterned on a same semiconductor device layer during a front-end-of-line (FEOL) process.Type: ApplicationFiled: September 30, 2020Publication date: March 31, 2022Inventors: Yu-Ann LAI, Ruo-Rung HUANG, Kun-Lung CHEN, Chun-Yi YANG, Chan-Hong CHERN
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Publication number: 20210372859Abstract: A circuit includes a temperature-sensitive voltage divider. The temperature-sensitive voltage divider includes a temperature-sensitive resistor and a second resistor having a first terminal coupled to a first terminal of the temperature-sensitive resistor. A temperature signal is generated at a first node coupled to the first terminal of the temperature-sensitive resistor. Detection logic is coupled to the first node to generate a detection signal responsive to the temperature signal.Type: ApplicationFiled: August 16, 2021Publication date: December 2, 2021Inventors: Chan-Hong CHERN, Kun-Lung CHEN, Ming Hsien TSAI
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Publication number: 20210281259Abstract: Devices, systems, and methods are provided for generating a high, dynamic voltage boost. An integrated circuit (IC) includes a driving circuit having a first stage and a second stage. The driving circuit is configured to provide an overdrive voltage. The IC also includes a charge pump circuit coupled between the first stage and the second stage. The charge pump circuit is configured generate a dynamic voltage greater than the overdrive voltage. The IC also includes a bootstrap circuit coupled to the charge pump circuit, configured to further dynamically boost the overdrive voltage of the driving circuit.Type: ApplicationFiled: May 24, 2021Publication date: September 9, 2021Inventors: Chan-Hong Chern, Tysh-Bin Liu, Kun-Lung Chen
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Patent number: 11092497Abstract: A circuit includes a temperature-sensitive voltage divider. The temperature-sensitive voltage divider includes a temperature-sensitive resistor and a second resistor having a first terminal coupled to a first terminal of the temperature-sensitive resistor. A temperature signal is generated at a first node coupled to the first terminal of the temperature-sensitive resistor. Detection logic is coupled to the first node to generate a detection signal responsive to the temperature signal.Type: GrantFiled: July 1, 2019Date of Patent: August 17, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITEDInventors: Chan-Hong Chern, Kun-Lung Chen, Ming Hsien Tsai
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Publication number: 20210226611Abstract: Various embodiments of the present application are directed towards a level shifter with temperature compensation. In some embodiments, the level shifter comprises a transistor, a first resistor, and a second resistor. The first resistor is electrically coupled from a first source/drain of the transistor to a supply node, and the second resistor is electrically coupled from a second source/drain of the transistor to a reference node. Further, the first and second resistors have substantially the same temperature coefficients and comprise group III-V semiconductor material. By having both the first and second resistors, the output voltage of the level shifter is defined by the resistance ratio of the resistors. Further, since the first and second resistors have the same temperature coefficients, temperature induced changes in resistance is largely cancelled out in the ratio and the output voltage is less susceptible to temperature induced change than the first and second resistors individually.Type: ApplicationFiled: April 5, 2021Publication date: July 22, 2021Inventors: Chan-Hong Chern, Kun-Lung Chen