Abstract: A chip structure is provided. The chip structure includes a substrate. The chip structure includes a conductive pad over the substrate. The chip structure includes a passivation layer covering the substrate and exposing the conductive pad. The chip structure includes a first etch stop layer over the passivation layer. The chip structure includes a first buffer layer over the first etch stop layer. The first etch stop layer and the first buffer layer are made of different materials. The chip structure includes a second etch stop layer over the first buffer layer. The second etch stop layer and the first buffer layer are made of different materials.

Abstract: A semiconductor device includes a first conductive layer, a second conductive layer, a third conductive layer, a first organic layer, a first inorganic layer and a first silicon-containing layer. The third conductive layer is disposed between and electrically isolated from the first conductive layer and the second conductive layer. The first organic layer continuously covers the first conductive layer and the third conductive layer. The first inorganic layer is disposed over the first organic layer. The first silicon-containing layer is inserted between the first organic layer and the first inorganic layer, wherein the second conductive layer is disposed on and disposed in the first organic layer, the first silicon-containing layer and the first inorganic layer, to electrically connect to the first conductive layer.

Abstract: A chip structure is provided. The chip structure includes a substrate. The chip structure includes an interconnect structure over the substrate. The chip structure includes a conductive pad over the interconnect structure. The chip structure includes a passivation layer covering the interconnect structure and exposing the conductive pad. The chip structure includes a first etch stop layer over the passivation layer. The chip structure includes a first buffer layer over the first etch stop layer. The first etch stop layer and the first buffer layer are made of different materials. The chip structure includes a second etch stop layer over the first buffer layer. The second etch stop layer and the first buffer layer are made of different materials. The chip structure includes a device element over the second etch stop layer.

Abstract: A method of forming a semiconductor device includes following steps. A first organic layer is formed to cover a first conductive layer. A first opening is formed in the first organic layer to expose a first surface of the first conductive layer. A first silicon layer is formed on a sidewall of the first opening and the first surface of the first conductive layer. A first dielectric layer is formed on the sidewall of the first opening and the first surface of the first conductive layer over the first silicon layer. By using a first mask, portions of the first silicon layer and the first dielectric layer on the first surface are simultaneously removed to expose the first surface, wherein after removing the portions of the first silicon layer and the first dielectric layer, the first dielectric layer covers a top surface of the first silicon layer.

Abstract: A chip structure is provided. The chip structure includes a substrate. The chip structure includes an interconnect structure over the substrate. The chip structure includes a conductive pad over the interconnect structure. The chip structure includes a passivation layer covering the interconnect structure and exposing the conductive pad. The chip structure includes a first etch stop layer over the passivation layer. The chip structure includes a first buffer layer over the first etch stop layer. The first etch stop layer and the first buffer layer are made of different materials. The chip structure includes a second etch stop layer over the first buffer layer. The second etch stop layer and the first buffer layer are made of different materials. The chip structure includes a device element over the second etch stop layer.

Abstract: A chip structure is provided. The chip structure includes a substrate. The chip structure includes an interconnect structure over the substrate. The chip structure includes a conductive pad over the interconnect structure. The chip structure includes a passivation layer covering the interconnect structure and exposing the conductive pad. The chip structure includes a first etch stop layer over the passivation layer. The chip structure includes a first buffer layer over the first etch stop layer. The chip structure includes a second etch stop layer over the first buffer layer. The chip structure includes a device element over the second etch stop layer.

Abstract: A chip structure is provided. The chip structure includes a substrate. The chip structure includes an interconnect structure over the substrate. The chip structure includes a conductive pad over the interconnect structure. The chip structure includes a passivation layer covering the interconnect structure and exposing the conductive pad. The chip structure includes a first etch stop layer over the passivation layer. The chip structure includes a first buffer layer over the first etch stop layer. The chip structure includes a second etch stop layer over the first buffer layer. The chip structure includes a device element over the second etch stop layer.

Abstract: A method of forming a semiconductor device includes following steps. A first organic layer is formed to cover a first conductive layer. A first opening is formed in the first organic layer to expose a first surface of the first conductive layer. A first silicon layer is formed on a sidewall of the first opening and the first surface of the first conductive layer. A first dielectric layer is formed on the sidewall of the first opening and the first surface of the first conductive layer over the first silicon layer. By using a first mask, portions of the first silicon layer and the first dielectric layer on the first surface are simultaneously removed to expose the first surface, wherein after removing the portions of the first silicon layer and the first dielectric layer, the first dielectric layer covers a top surface of the first silicon layer.

Abstract: A semiconductor device includes a first conductive layer, an organic layer and a silicon layer. The first conductive layer includes a first surface. The organic layer is disposed over the first surface of the first conductive layer. The silicon layer is disposed over the organic layer and extended onto and in contact with the first surface of the first conductive layer.

Abstract: A semiconductor device includes a first conductive layer, an organic layer and a silicon layer. The first conductive layer includes a first surface. The organic layer is disposed over the first surface of the first conductive layer. The silicon layer is disposed over the organic layer and extended onto and in contact with the first surface of the first conductive layer.

Abstract: Semiconductor devices and methods of forming the same are disclosed. One of the semiconductor devices includes a first conductive layer, an organic layer, a silicon layer, a magnetic layer and a second conductive layer. The organic layer is disposed over and exposes a portion of the first conductive layer. The silicon layer is disposed on and in contact with the organic layer. The magnetic layer is disposed over the first conductive layer. The second conductive layer is disposed over the organic layer and the magnetic layer to electrically connect the first conductive layer.

Abstract: Semiconductor devices and methods of forming the same are disclosed. One of the semiconductor devices includes a first conductive layer, an organic layer, a silicon layer, a magnetic layer and a second conductive layer. The organic layer is disposed over and exposes a portion of the first conductive layer. The silicon layer is disposed on and in contact with the organic layer. The magnetic layer is disposed over the first conductive layer. The second conductive layer is disposed over the organic layer and the magnetic layer to electrically connect the first conductive layer.

Abstract: A motion recognition device includes a sensing unit and a processing unit. The sensing unit generates a sense signal in response to a body motion occurring at a specific position on a user's body, wherein the sense signal includes a first sense signal portion and a second sense signal portion different from the first sense signal portion, and the body motion belongs to a motion segment of a motion type. The processing unit processes the sense signal to generate a motion parameter signal structure including a fusion signal of the first and the second sense signal portions, and recognizes the specific position to determine an effective reference signal for recognition of the motion type based on the motion parameter signal structure.

Abstract: A motion recognition device includes a sensing unit and a processing unit. The sensing unit generates a sense signal in response to a body motion occurring at a specific position on a user's body, wherein the sense signal includes a first sense signal portion and a second sense signal portion different from the first sense signal portion, and the body motion belongs to a motion segment of a motion type. The processing unit processes the sense signal to generate a motion parameter signal structure including a fusion signal of the first and the second sense signal portions, and recognizes the specific position to determine an effective reference signal for recognition of the motion type based on the motion parameter signal structure.

Abstract: The invention provides a polishing pad suitable for planarizing at least one of semiconductor, optical and magnetic substrates. The polishing pad is a cast polyurethane polymeric matrix formed from an isocyanate-terminated molecule and a curative agent. The cast polyurethane polymeric matrix contains 4.2 to 7.5 weight percent fluid-filled microspheres in the isocyanate-terminated molecule. The fluid-filled-microspheres is polymeric and has an average diameter of 10 to 80 ?m and the polishing pad having a conditioner sensitivity (CS) of 0 to 2.6.

Abstract: The invention provides a polishing pad suitable for planarizing at least one of semiconductor, optical and magnetic substrates. The polishing pad is a cast polyurethane polymeric matrix formed from an isocyanate-terminated molecule and a curative agent. The cast polyurethane polymeric matrix contains 4.2 to 7.5 weight percent fluid-filled microspheres in the isocyanate-terminated molecule. The fluid-filled-microspheres is polymeric and has an average diameter of 10 to 80 ?m and the polishing pad having a conditioner sensitivity (CS) of 0 to 2.6.

Abstract: Control methods for a cell phone are provided upon occurrence of a particular event, which receive a contact-related information from a touch screen of the cell phone, analyze the contact-related information to identify the contact position, the number of contact objects, or a gesture, to determine a further step to deal with the particular event. The particular event may include receipt of a call, sounding of an alarm of the cell phone, displaying of a short message on the touch screen, receipt of an interrupting call, or a standby mode of the cell phone.

Abstract: A navigation system includes a touch screen for receiving a touch input and displaying a navigation map, mode-switching means for issuing a mode-switching command to switch the navigation system into an input mode, a memory for storing a database, and a controller to recognize a handwriting input or a gesture input to acquire an input information, search the database for a facility information corresponding to the input information, and show facilities represented by the facility information in the navigation map.

Abstract: A sensing method for a capacitive touch panel includes charging a measure capacitor, setting the voltage across a mutual capacitor at the intersection of two traces of the capacitive touch panel, and then injecting partial charges of the measure capacitor into the mutual capacitor. When the intersection is touched, the capacitance value of the mutual capacitor is changed, and consequently the amount of charges injected into the mutual capacitor is changed. Hence, the voltage of the measure capacitor could be detected to determine whether or not the intersection is touched.

Abstract: A sensing method for a capacitive touch panel includes charging a measure capacitor, setting the voltage across a mutual capacitor at the intersection of two traces of the capacitive touch panel, and then injecting partial charges of the measure capacitor into the mutual capacitor. When the intersection is touched, the capacitance value of the mutual capacitor is changed, and consequently the amount of charges injected into the mutual capacitor is changed. Hence, the voltage of the measure capacitor could be detected to determine whether or not the intersection is touched.