Patents by Inventor KUN-MO LIN

KUN-MO LIN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11725278
    Abstract: A system and method for plasma enhanced deposition processes. An exemplary semiconductor manufacturing system includes a susceptor configured to hold a semiconductor wafer and a sector disposed above the susceptor. The sector includes a first plate and an overlying second plate, operable to form a plasma there between. The first plate includes a plurality of holes extending through the first plate, which vary in at least one of diameter and density from a first region of the first plate to a second region of the first plate.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: August 15, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kun-Mo Lin, Yi-Hung Lin, Jr-Hung Li, Tze-Liang Lee, Ting-Gang Chen, Chung-Ting Ko
  • Publication number: 20200123656
    Abstract: A system and method for plasma enhanced deposition processes. An exemplary semiconductor manufacturing system includes a susceptor configured to hold a semiconductor wafer and a sector disposed above the susceptor. The sector includes a first plate and an overlying second plate, operable to form a plasma there between. The first plate includes a plurality of holes extending through the first plate, which vary in at least one of diameter and density from a first region of the first plate to a second region of the first plate.
    Type: Application
    Filed: December 20, 2019
    Publication date: April 23, 2020
    Inventors: Kun-Mo LIN, Yi-Hung LIN, Jr-Hung LI, Tze-Liang LEE, Ting-Gang CHEN, Chung-Ting KO
  • Patent number: 10519545
    Abstract: A system and method for plasma enhanced deposition processes. An exemplary semiconductor manufacturing system includes a susceptor configured to hold a semiconductor wafer and a sector disposed above the susceptor. The sector includes a first plate and an overlying second plate, operable to form a plasma there between. The first plate includes a plurality of holes extending through the first plate, which vary in at least one of diameter and density from a first region of the first plate to a second region of the first plate.
    Type: Grant
    Filed: May 31, 2016
    Date of Patent: December 31, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kun-Mo Lin, Yi-Hung Lin, Jr-Hung Li, Tze-Liang Lee, Ting-Gang Chen, Chung-Ting Ko
  • Patent number: 10269573
    Abstract: A device includes a pedestal. The pedestal includes a ground electrode, a central portion, and a peripheral portion. The ground electrode includes a top surface from which the peripheral portion is projected, thereby having a height difference between the central portion and the peripheral portion.
    Type: Grant
    Filed: March 31, 2014
    Date of Patent: April 23, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Kun-Mo Lin, Keith Kuang-Kuo Koai, Chih-Tsung Lee, Victor Y. Lu, Yi-Hung Lin
  • Publication number: 20170342561
    Abstract: A system and method for plasma enhanced deposition processes. An exemplary semiconductor manufacturing system includes a susceptor configured to hold a semiconductor wafer and a sector disposed above the susceptor. The sector includes a first plate and an overlying second plate, operable to form a plasma there between. The first plate includes a plurality of holes extending through the first plate, which vary in at least one of diameter and density from a first region of the first plate to a second region of the first plate.
    Type: Application
    Filed: May 31, 2016
    Publication date: November 30, 2017
    Inventors: Kun-Mo LIN, Yi-Hung LIN, Jr-Hung LI, Tze-Liang LEE, Ting-Gang CHEN, Chung-Ting KO
  • Publication number: 20150279632
    Abstract: A device includes a pedestal. The pedestal includes a ground electrode, a central portion, and a peripheral portion. The ground electrode includes a top surface from which the peripheral portion is projected, thereby having a height difference between the central portion and the peripheral portion.
    Type: Application
    Filed: March 31, 2014
    Publication date: October 1, 2015
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: KUN-MO LIN, KEITH KUANG-KUO KOAI, CHIH-TSUNG LEE, VICTOR Y. LU, YI-HUNG LIN