Patents by Inventor KUN-MU LI

KUN-MU LI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150236157
    Abstract: A transistor device includes a gate structure disposed over a channel region of a semiconductor substrate. A source/drain recess is arranged in the semiconductor substrate alongside the gate structure. A doped silicon-germanium (SiGe) region is disposed within the source/drain recess and has a doping type which is opposite to that of the channel. An un-doped SiGe region is also disposed within the source/drain recess. The un-doped SiGe region underlies the doped SiGe region and comprises different germanium concentrations at different locations within the source/drain recess.
    Type: Application
    Filed: February 14, 2014
    Publication date: August 20, 2015
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsz-Mei Kwok, Hsueh-Chang Sung, Kun-Mu Li, Chii-Horng Li, Tze-Liang Lee
  • Publication number: 20150228724
    Abstract: An integrated circuit structure includes a gate stack over a semiconductor substrate, and an opening extending into the semiconductor substrate, wherein the opening is adjacent to the gate stack. A first silicon germanium region is disposed in the opening, wherein the first silicon germanium region has a first germanium percentage. A second silicon germanium region is overlying the first silicon germanium region, wherein the second silicon germanium region has a second germanium percentage higher than the first germanium percentage. A metal silicide region is over and in contact with the second silicon germanium region.
    Type: Application
    Filed: April 20, 2015
    Publication date: August 13, 2015
    Inventors: Tsz-Mei Kwok, Kun-Mu Li, Hsueh-Chang Sung, Chii-Horng Li, Tze-Liang Lee
  • Publication number: 20150179796
    Abstract: The present disclosure relates to a transistor device having a strained source/drain region comprising a strained inducing material having a discontinuous germanium concentration profile. In some embodiments, the transistor device has a gate structure disposed onto a semiconductor substrate. A source/drain region having a strain inducing material is disposed along a side of the gate structure within a source/drain recess in the semiconductor substrate. The strain inducing material has a discontinuous germanium concentration profile along a line extending from a bottom surface of the source/drain recess to a top surface of the source/drain recess. The discontinuous germanium concentration profile provides improved strain boosting and dislocation propagation.
    Type: Application
    Filed: December 19, 2013
    Publication date: June 25, 2015
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsueh-Chang Sung, Tsz-Mei Kwok, Kun-Mu Li, Tze-Liang Lee, Chii-Horng Li
  • Patent number: 9012964
    Abstract: An integrated circuit structure includes a gate stack over a semiconductor substrate, and an opening extending into the semiconductor substrate, wherein the opening is adjacent to the gate stack. A first silicon germanium region is disposed in the opening, wherein the first silicon germanium region has a first germanium percentage. A second silicon germanium region is overlying the first silicon germanium region, wherein the second silicon germanium region has a second germanium percentage higher than the first germanium percentage. A metal silicide region is over and in contact with the second silicon germanium region.
    Type: Grant
    Filed: August 9, 2013
    Date of Patent: April 21, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsz-Mei Kwok, Kun-Mu Li, Hsueh-Chang Sung, Chii-Horng Li, Tze-Liang Lee
  • Publication number: 20150061024
    Abstract: An integrated circuit structure includes a gate stack over a semiconductor substrate, and a silicon germanium region extending into the semiconductor substrate and adjacent to the gate stack. The silicon germanium region has a top surface, with a center portion of the top surface recessed from edge portions of the top surface to form a recess. The edge portions are on opposite sides of the center portion.
    Type: Application
    Filed: September 3, 2013
    Publication date: March 5, 2015
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kun-Mu Li, Tsz-Mei Kwok, Hsueh-Chang Sung, Chii-Horng Li, Tze-Liang Lee
  • Publication number: 20150048417
    Abstract: An integrated circuit structure includes a gate stack over a semiconductor substrate, and an opening extending into the semiconductor substrate, wherein the opening is adjacent to the gate stack. A first silicon germanium region is in the opening, wherein the first silicon germanium region has a first germanium percentage. A second silicon germanium region is over the first silicon germanium region, wherein the second silicon germanium region has a second germanium percentage higher than the first germanium percentage. A third silicon germanium region is over the second silicon germanium region, wherein the third silicon germanium region has a third germanium percentage lower than the second germanium percentage.
    Type: Application
    Filed: August 16, 2013
    Publication date: February 19, 2015
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsz-Mei Kwok, Kun-Mu Li, Hsueh-Chang Sung, Chii-Horng Li, Tze-Liang Lee
  • Publication number: 20150041852
    Abstract: An integrated circuit structure includes a gate stack over a semiconductor substrate, and an opening extending into the semiconductor substrate, wherein the opening is adjacent to the gate stack. A first silicon germanium region is disposed in the opening, wherein the first silicon germanium region has a first germanium percentage. A second silicon germanium region is overlying the first silicon germanium region, wherein the second silicon germanium region has a second germanium percentage higher than the first germanium percentage. A metal silicide region is over and in contact with the second silicon germanium region.
    Type: Application
    Filed: August 9, 2013
    Publication date: February 12, 2015
    Applicant: Taiwan Semiconductor Manufacturing Comapny, Ltd.
    Inventors: Tsz-Mei Kwok, Kun-Mu Li, Hsueh-Chang Sung, Chii-Horng Li, Tze-Liang Lee
  • Publication number: 20150021696
    Abstract: An integrated circuit structure includes a gate stack over a semiconductor substrate, and an opening extending into the semiconductor substrate, wherein the opening is adjacent to the gate stack. A first silicon germanium region is disposed in the opening, wherein the first silicon germanium region has a first germanium percentage. A second silicon germanium region is over the first silicon germanium region. The second silicon germanium region comprises a portion in the opening. The second silicon germanium region has a second germanium percentage greater than the first germanium percentage. A silicon cap substantially free from germanium is over the second silicon germanium region.
    Type: Application
    Filed: July 17, 2013
    Publication date: January 22, 2015
    Inventors: Hsueh-Chang Sung, Tsz-Mei Kwok, Kun-Mu Li, Tze-Liang Lee, Chii-Horng Li
  • Publication number: 20150021688
    Abstract: An integrated circuit structure include a semiconductor substrate, a gate stack over the semiconductor substrate, and an opening extending into the semiconductor substrate, wherein the opening is adjacent to the gate stack. A silicon germanium region is disposed in the opening, wherein the silicon germanium region has a first p-type impurity concentration. A silicon cap substantially free from germanium is overlying the silicon germanium region. The silicon cap has a second p-type impurity concentration greater than the first p-type impurity concentration.
    Type: Application
    Filed: July 16, 2013
    Publication date: January 22, 2015
    Inventors: Hsueh-Chang Sung, Tsz-Mei Kwok, Kun-Mu Li, Tze-Liang Lee, Chii-Horng Li
  • Patent number: 8815713
    Abstract: A method includes forming a gate stack over a semiconductor substrate, forming an opening in the semiconductor substrate and adjacent to the gate stack, and performing a first epitaxy to grow a first semiconductor layer in the first opening. An etch-back is performed to reduce a thickness of the first semiconductor layer. A second epitaxy is performed to grow a second semiconductor layer over the first semiconductor layer. The first and the second semiconductor layers have different compositions.
    Type: Grant
    Filed: November 7, 2012
    Date of Patent: August 26, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsueh-Chang Sung, Tsz-Mei Kwok, Kuan-Yu Chen, Kun-Mu Li
  • Publication number: 20140127886
    Abstract: A method includes forming a gate stack over a semiconductor substrate, forming an opening in the semiconductor substrate and adjacent to the gate stack, and performing a first epitaxy to grow a first semiconductor layer in the first opening. An etch-back is performed to reduce a thickness of the first semiconductor layer. A second epitaxy is performed to grow a second semiconductor layer over the first semiconductor layer. The first and the second semiconductor layers have different compositions.
    Type: Application
    Filed: November 7, 2012
    Publication date: May 8, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hsueh-Chang Sung, Tsz-Mei Kwok, Kuan-Yu Chen, Kun-Mu Li
  • Publication number: 20130065025
    Abstract: A substrate having animated flashing figures, applications thereof, and a manufacturing method of the same are revealed. A reflective film with an electroplated layer on a surface is covered over the base material. Then at least two figures are printed on the reflective film to form a printed layer. The figures are cut into strips and then the strips are arranged alternatively. Finally, a surface grating layer is arranged over the printed layer. Through the combination of the reflective film, the printed layer formed by staggered strips of the figures, and the surface grating layer, figures on a surface of the substrate show an animated flashing effect. The substrate can be applied to various products such as containers, trays, eyeglass frames, watch bands, etc.
    Type: Application
    Filed: September 9, 2011
    Publication date: March 14, 2013
    Inventor: KUN-MU LI
  • Publication number: 20120187597
    Abstract: A substrate capable of producing 3D pattern having colored dazzle light effect and a method of producing pattern and fabricating finished product are provided, in which plastic foaming sheet is selected as base material and reflection film having its surface electroplated is overlaid thereon. Then, embossing process is conducted to form concave-convex veins, and finally printing is conducted to form a print-layer thereon, so that the surface of the substrate possesses a 3D pattern having colored dazzle light effect. This substrate can be utilized in products as container, tray, eyeglass frame or watchstrap.
    Type: Application
    Filed: January 20, 2011
    Publication date: July 26, 2012
    Inventor: KUN-MU LI