Abstract: A semiconductor process wafer having substantially co-planar active areas and a laser marked area in an adjacent inactive area and method for forming the same to eliminate a step height and improve a subsequent patterning process over the active areas wherein an inactive area trench is formed overlying the laser marked area in parallel with formation of STI trenches in the active area whereby the active areas and the inactive area are formed substantially co-planar without a step height.

Abstract: An automatic method to maintain and correct overlay in the fabrication of integrated circuits is described. An overlay control table is automatically generated for lots run through a process tool. An overlay correction is calculated from the overlay control table and sent to the process tool for real-time or manual overlay correction.

Abstract: A method for fabricating a microelectronic product and a system for fabricating the microelectronic product each employ an in-line automatic photolithographic processing and overlay registration measurement for a pair of pilot lots of a new product order, prior to in-line automatic processing of an additional new product order lot within a photolithographic process tool. The method and the system provide for efficient production of new product order lots, absent need for an independent pilot lot qualification method or system.

Abstract: A semiconductor process wafer having substantially co-planar active areas and a laser marked area in an adjacent inactive area and method for forming the same to eliminate a step height and improve a subsequent patterning process over the active areas wherein an inactive area trench is formed overlying the laser marked area in parallel with formation of STI trenches in the active area whereby the active areas and the inactive area are formed substantially co-planar without a step height.

Abstract: An automatic method to maintain and correct overlay in the fabrication of integrated circuits is described. An overlay control table is automatically generated for lots run through a process tool. An overlay correction is calculated from the overlay control table and sent to the process tool for real-time or manual overlay correction.

Abstract: A method for fabricating a microelectronic product and a system for fabricating the microelectronic product each employ an in-line automatic photolithographic processing and overlay registration measurement for a pair of pilot lots of a new product order, prior to in-line automatic processing of an additional new product order lot within a photolithographic process tool. The method and the system provide for efficient production of new product order lots, absent need for an independent pilot lot qualification method or system.

Abstract: A method for determining an overlay registration correction for a new product lot of a microelectronic product type with respect to a specific alignment tool within a foundry facility first provides for determining: (1) a first average historic overlay registration correction for historic product lots of the new product lot type with respect to the specific alignment tool; and (2) a second average historic overlay registration correction with respect to product lots of any product type with respect to the specific alignment tool. The overlay registration correction is determined as the sum of: (1) an overlay registration correction for an immediately preceding layer within the new product lot, if present; (2) a factor derived from the first average historic overlay registration correction; and (3) a factor derived from the second average historic overlay registration correction.

Abstract: A method for determining an overlay registration correction for a new product lot of a microelectronic product type with respect to a specific alignment tool within a foundry facility first provides for determining: (1) a first average historic overlay registration correction for historic product lots of the new product lot type with respect to the specific alignment tool; and (2) a second average historic overlay registration correction with respect to product lots of any product type with respect to the specific alignment tool. The overlay registration correction is determined as the sum of: (1) an overlay registration correction for an immediately preceding layer within the new product lot, if present; (2) a factor derived from the first average historic overlay registration correction; and (3) a factor derived from the second average historic overlay registration correction.

Abstract: An optical inspection system for detecting defects on the surface of a semiconductor wafer includes two light sources and two light receivers mounted as a common assembly which is rotated such that two curtains of light and corresponding linear photosensor arrays circularly scan the wafer surface. The reflected light is analyzed to determine the presence of surface defects. Marks applied to the wafer surface provide amplitude and timing references used to adjust and synchronize the analyzed signals.

Abstract: The two dimensional intensity profile of radiation applied to a semiconductor wafer during photolithography is controlled by passing the radiation beam through an attenuating member before the beam is imaged by a mask onto the wafer. The attenuating member is preferably ring shaped and is formed of a semi-transparent material such as Mo Bi Si O4, or a material that is partially reflective of the radiation.

Abstract: A method of overlaying two images and from this overlay observe and measure the accuracy of the alignment of the wafer. Wafer misalignment can be readily corrected based on the results of these observations. Alignment marks are provided on the surface of the wafer that is being validated for accuracy of alignment. The position of this mark relative to a pattern provided on the surface of a control wafer is measured and forms an indication of the alignment of the wafer.

Abstract: A mask, which does not require additional reticles, and a method of using the mask for recovering alignment marks in a wafer after an inter-level dielectric layer has been planarized and a second layer of metal has been deposited on the planarized inter-level dielectric layer are described. An alignment mark protection pattern and a clearout window pattern are sub-divided so they can be formed from a first and a second mask element. These mask elements can be formed in the peripheral region of the reticle used to pattern the device region of the wafer. The mask elements are used to expose the alignment mark protection pattern in a first layer of photoresist and the clearout window pattern in a second layer of photoresist.

Abstract: A mask, which does not require additional reticles, and a method of using the mask for recovering alignment marks in a wafer after an inter-level dielectric layer has been planarized and a second layer of metal has been deposited on the planarized inter-level dielectric layer are described. An alignment mark protection pattern and a clearout window pattern are sub-divided so they can be formed from a first and a second mask element. These mask elements can be formed in the peripheral region of the reticle used to pattern the device region of the wafer. The mask elements are used to expose the alignment mark protection pattern in a first layer of photoresist and the clearout window pattern in a second layer of photoresist.