Abstract: A low parasitic inductance power module having staggered, interleaving busbars, including: at least one base extending a long a length direction, the base having at least one current input busbar and at least one current output busbar, the current input busbar and the current out busbar being formed with a plurality of interdigitated contact terminals, respectively; a first unit comprising a first circuit base portion disposed on the base along the width direction, on the first circuit base portion being disposed a plurality of first power devices; and a second unit, whereby when current flows through the units and the individual interdigitated contact terminals, individual inductances produced thereby are cancelled with each other, whereby overall parasitic inductance of the power module is reduced.

Abstract: A low parasitic inductance power module featuring staggered, interleaving conductive members, including: at least one base extending in a length direction, at least one input bus-bar and at least one output bus-bar being disposed on the base; a first unit including a first circuit base portion disposed on the base along the width direction, a plurality of first power devices being disposed on the first circuit base portion, each of the first power devices having paralleled first current input ends and paralleled first current output ends; the first current input ends or the current output ends being conductively connected to the first circuit base portion; and a second unit. The units are serially connected to the bus-bars via staggered, interleaving input conductive members and output conductive members whereby individual inductances generated are mutually counteracted, thus reducing the overall parasitic inductance.

Abstract: A power module includes two power input terminals, two main substrates, a plurality of first switches, a plurality of second switches, and a bridge main unit. The bridge main unit is across the two main substrates, and includes a first bridge subunit and a second bridge subunit. Each of the first bridge subunit and the second bridge subunit includes a first conducting region on a bottom surface, and a second conducting region and a third conducting region on a top surface. The first conducting region transmits a current signal of a current path of a switch circuit formed by the power input terminals, the first switches, and the second switches. The second conducting region is connected to the control terminals of the first switches and the second switches. The third conducting region is connected to the output terminals of the first switches and the second switches.

Abstract: Disclosed is a flip-chip packaged power transistor module having a built-in gate driver, for outputting a high-power signal of at least tens of amperes, the module including at least one power transistor die which has an active side where at least one source pin, at least one drain pin and at least one gate pin are exposed; a ceramic substrate body which has a conducting junction side and a heat spreading side, a minimal spacing of the gate bonding pad from at least one of the source bonding pad or the drain bonding pad being less than 500 ?m, whereby parasitic inductance generated therebetween is reduced; at least one gate driver which has at least one gate pin configured to be soldered to the gate bonding pad, and at least one gate drive pin which corresponds to the gate pin and is configured to be soldered to the drive bonding pad.

Abstract: A low parasitic inductance power module featuring staggered interleaving conductive members, including: at least one base extending in a length direction; a substrate on which at least one input bus bar and at least one output bus bar are provided; a first unit including a first circuit base portion disposed on the base in a width direction, a plurality of first power devices being disposed on the first circuit base portion, each first power device having a first current input end and a first current output end which are parallel connected, the first current input end or the first current output end being conducted to the first circuit base portion; and a second unit. The units are serially-connected to the bus bars via input conductive members and output conductive members arrayed in a staggered interleaving mode, whereby to create individual inductances counteracting with each other, reducing overall parasitic inductance.

Abstract: A compact single-to-balanced bandpass filter is proposed in this invention. Firstly, a pre-design circuit is presented, which is composed of an inductive coupled-line (ICL) bandpass filter and an out-of-phase capacitive coupled-line (CCL) bandpass filter. A novel compact circuit with three coupled lines configuration, derived from the pre-design circuit, is then proposed for miniaturizing the single-to-balanced bandpass filter. In order to verify the feasibility of the proposed structure, a 2.4 GHz multilayer ceramic chip type single-to-balanced bandpass filter with size of 2.0 mm×1.2 mm×0.7 mm is developed. The filter is designed by using circuit simulation as well as full-wave electromagnetic (EM) simulation softwares, and fabricated by the use of low-temperature co-fire ceramic (LTCC) technology. The measured results agree quite well with the simulated. According to the measurement results, the maximum insertion loss is 1.