Patents by Inventor Kun Wu

Kun Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7265038
    Abstract: A copper filled damascene structure and method for forming the same the method including providing a substrate comprising a semiconductor substrate; forming an insulator layer on the substrate; forming a damascene opening through a thickness portion of the insulator layer; forming a diffusion barrier layer to line the damascene opening; forming a first seed layer overlying the diffusion barrier; plasma treating the first seed layer in-situ with a first treatment plasma comprising plasma source gases selected from the group consisting of argon, nitrogen, hydrogen, and NH3; forming a second seed layer overlying the first seed layer; forming a copper layer overlying the second seed layer according to an electro-chemical plating (ECP) process to fill the damascene opening; and, planarizing the copper layer to form a metal interconnect structure.
    Type: Grant
    Filed: November 25, 2003
    Date of Patent: September 4, 2007
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ping-Kun Wu, Horng-Huei Tseng, Chine-Gie Lo, Chao-Hsiung Wang, Shau-Lin Shue
  • Publication number: 20070195199
    Abstract: A method includes calculating a mean of a plurality of pixels of a motion window, calculating a pixel amount of pixels similar to a center pixel, calculating a variance of the pixels, determining whether a difference between the center pixel and the mean is greater than a first predetermined value, determining whether the pixel amount similar to the center pixel is greater than a second predetermined value if the difference between the center pixel and the mean is not greater than the first predetermined value, determining whether the variance is smaller than a threshold value if the pixel amount similar to the center pixel is not greater than the second predetermined value, and filtering the center pixel according to a result of determining whether the variance is smaller than the threshold value. Finally, temporal weighted mean filters involving motion estimation are used for motion compensation in images after spatial filtering.
    Type: Application
    Filed: January 15, 2007
    Publication date: August 23, 2007
    Inventors: Chao-Ho Chen, Ming-Kun Wu
  • Publication number: 20070196031
    Abstract: A method for reducing image noise includes calculating a first pixel amount of pixels that are similar to each other in a first number neighbor of a center pixel in a motion window, determining whether the first pixel amount of pixels that are similar to each other in the first number neighbor is greater than a first predetermined value, and using a mean of those pixels of the first pixel amount of pixels that are similar to each other in the first number neighbor to restore the center pixel of the motion window if the first pixel amount of pixels is greater than the first predetermined value. The method includes determining whether a second pixel amount of pixels that are similar to the center pixel is greater than a second predetermined value if the first pixel amount of pixels is not greater than the first predetermined value.
    Type: Application
    Filed: December 25, 2006
    Publication date: August 23, 2007
    Inventors: Chao-Ho Chen, Ming-Kun Wu
  • Patent number: 7208815
    Abstract: In preferred embodiments of the present invention, a method of forming CMOS devices using SOI and hybrid substrate orientations is described. In accordance with a preferred embodiment, a substrate may have multiple crystal orientations. One logic gate in the substrate may comprise at least one N-FET on one crystal orientation and at least one P-FET on another crystal orientation. Another logic gate in the substrate may comprise at least one N-FET and at least one P-FET on the same orientation. Alternative embodiments further include determining the preferred cleavage planes of the substrates and orienting the substrates relative to each other in view of their respective preferred cleavage planes. In a preferred embodiment, the cleavage planes are not parallel.
    Type: Grant
    Filed: November 15, 2004
    Date of Patent: April 24, 2007
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Wei Chen, Ping-Kun Wu, Chao-Hsiung Wang, Fu-Liang Yang, Chenming Hu
  • Publication number: 20070075428
    Abstract: An integrated circuit device comprising a partially embedded and encapsulated damascene structure and method for forming the same to improve adhesion to an overlying dielectric layer, the integrated circuit device including a conductive material partially embedded in an opening formed in a dielectric layer; wherein said conductive material is encapsulated with a first barrier layer comprising sidewall and bottom portions and a second barrier layer covering a top portion, said conductive material and first barrier layer sidewall portions extending to a predetermined height above an upper surface of the dielectric layer to form a partially embedded damascene.
    Type: Application
    Filed: September 30, 2005
    Publication date: April 5, 2007
    Inventors: Chao-Hsiung Wang, Ping-Kun Wu
  • Patent number: 7168938
    Abstract: A nylon zipper has two fastener structures. Each fastener structure has a plurality of nylon gripper elements. Each nylon gripper element has at least one side including a concave portion. A seaming wire for seaming the zipper to a cross strip is embedded in the concave portion. Thereby when pulling a pull head, the seaming wire will not rubber the cross strip. Moreover, a threaded rod device of a nylon zipper comprises two parallel threaded rods. Each threaded rod has threads. One of the threaded rod has a plurality of tips arranged in recesses between each two threads for forming concave portions and convex portions on nylon gripper elements of the fastener structures of the nylon zipper at the same time.
    Type: Grant
    Filed: August 6, 2003
    Date of Patent: January 30, 2007
    Inventor: Hsin-Kun Wu
  • Patent number: 7139990
    Abstract: A sub-circuit based extraction method which extracts a multi-finger MOS transistor directly as a sub-circuit is described. By adding three marking layers, the method provides the layout extracted netlist with a complete list of device geometric parameters corresponding to the device properties as presented in the sub-circuit model based schematic netlist. By performing a layout-versus-schematic comparison based on all geometric parameters extracted, the layout checking is performed in a complete and accurate way where each device parameter is checked against the corresponding design schematic. This complete and accurate geometric parameter comparison enhances the confidence level of the layout physical verification.
    Type: Grant
    Filed: March 23, 2004
    Date of Patent: November 21, 2006
    Assignee: International Business Machines Corporation
    Inventors: Raminderpal Singh, Yue Tan, Jean-Oliver Plouchart, Lawrence F. Wagner, Jr., Mohamed Talbi, John M. Safran, Kun Wu
  • Patent number: 7105897
    Abstract: This invention discloses a method and a semiconductor structure for integrating at least one bulk device and at least one silicon-on-insulator (SOI) device. The semiconductor structure includes a first substrate having an SOI area and a bulk area, on which the bulk device is formed; an insulation layer formed on the first substrate in the SOI area; and a second substrate, on which the SOI device is formed, stacked on the insulation layer. The surface of the first substrate is not on the substantially same plane as the surface of the second substrate.
    Type: Grant
    Filed: October 28, 2004
    Date of Patent: September 12, 2006
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Hao-Yu Chen, Fu-Liang Yang, Hung-Wei Chen, Ping-Kun Wu, Chao-Hsiung Wang
  • Patent number: 7102874
    Abstract: The present invention describes an intermediate for use in a capacitive printed circuit board (PCB), which relates to a capacitive apparatus and manufacturing method for a built-in capacitor with a non-symmetrical electrode used to reduce inaccuracy of the error compression alignment on laminates. The invention employs a plurality of different sized metal laminates stacked for a built-in capacitor to achieve a high-precise capacitor PCB. More particularly, the invention can raise the capability of noise-immunity of a capacitive PCB applied to high frequency/speed modules and systems, and also provides precise capacitance to regular circuit design for the need of compact package and high-precise capacitance in the future.
    Type: Grant
    Filed: July 21, 2004
    Date of Patent: September 5, 2006
    Assignee: Industrial Technology Research Institute
    Inventors: Uei-Ming Jow, Ying-Jiunn Lai, Chun-Kun Wu, Pel-Shen Wei, Chang-Sheng Chen, Ching-Liang Weng
  • Patent number: 7073211
    Abstract: A hydraulic plumber's friend has a cylindrical body, a lid, a compression assembly, a tapered end cap and a nozzle assembly. The cylindrical body has an open bottom and holds water to be injected into a clogged pipe. The compression assembly has a drive shaft and a piston mounted slidably in the cylindrical body. The tapered end cap is mounted on the open bottom of the cylindrical body and has a transverse partition, a tapered body and a spout. The nozzle assembly has a valve having a cylindrical disk mounted slidably in the spout and having a closed top, an open bottom, a cylindrical sidewall and multiple charging holes, a valve stem and a spring. When the charging holes are uncovered, water flows. The nozzle is mounted on the cylindrical disk and seals and directs water into an opening in a clogged pipe.
    Type: Grant
    Filed: December 14, 2005
    Date of Patent: July 11, 2006
    Assignee: Sam Rock Industrial Co., Ltd.
    Inventor: Kuei-Kun Wu
  • Publication number: 20060097316
    Abstract: This invention discloses a method and a semiconductor structure for integrating at least one bulk device and at least one silicon-on-insulator (SOI) device. The semiconductor structure includes a first substrate having an SOI area and a bulk area, on which the bulk device is formed; an insulation layer formed on the first substrate in the SOI area; and a second substrate, on which the SOI device is formed, stacked on the insulation layer. The surface of the first substrate is not on the substantially same plane as the surface of the second substrate.
    Type: Application
    Filed: October 28, 2004
    Publication date: May 11, 2006
    Inventors: Hao-Yu Chen, Fu-Liang Yang, Hung-Wei Chen, Ping-Kun Wu, Chao-Hsiung Wang
  • Publication number: 20060077813
    Abstract: A method and disc reading device for detecting an unbalanced disc are disclosed. The disc reading device includes a first sensor, a second sensor, a cache memory, an operating unit and a data table. The first sensor and the second sensor respectively detect a first parameter and a second parameter when the disc reading apparatus driving the disc at a predetermined voltage. When the first parameter is detected as being equal to a first predetermined value, the cache memory records the second parameter as a first corresponding value. When the second parameter is detected as being equal to a second predetermined value, the cache memory records the second parameter as a second corresponding value. The operating unit calculates a difference between the first and the second corresponding values to obtain the unbalance status.
    Type: Application
    Filed: September 1, 2005
    Publication date: April 13, 2006
    Inventors: Cheng-Chieh Chuang, Sung-Kun Wu
  • Publication number: 20060049460
    Abstract: In preferred embodiments of the present invention, a method of forming CMOS devices using SOI and hybrid substrate orientations is described. In accordance with a preferred embodiment, a substrate may have multiple crystal orientations. One logic gate in the substrate may comprise at least one N-FET on one crystal orientation and at least one P-FET on another crystal orientation. Another logic gate in the substrate may comprise at least one N-FET and at least one P-FET on the same orientation. Alternative embodiments further include determining the preferred cleavage planes of the substrates and orienting the substrates relative to each other in view of their respective preferred cleavage planes. In a preferred embodiment, the cleavage planes are not parallel.
    Type: Application
    Filed: November 15, 2004
    Publication date: March 9, 2006
    Inventors: Hung-Wei Chen, Ping-Kun Wu, Chao-Hsiung Wang, Fu-Liang Yang, Chenming Hu
  • Publication number: 20050263891
    Abstract: A damascene structure for semiconductor devices is provided. In an embodiment, the damascene structure includes trenches formed over vias that electrically couple the trenches to an underlying conductive layer such that the trenches have varying widths. The vias are lined with a first barrier layer. The first barrier layers along the bottom of vias are removed such that a recess formed in the underlying conductive layer. The recesses formed along the bottom of vias are such that the recess below narrower trenches is greater than the recess formed below wider trenches. In another embodiment, a second barrier layer may then be formed over the first barrier layer. In this embodiment, a portion of the conductive layer may be interposed between the first barrier layer and the second barrier layer.
    Type: Application
    Filed: April 7, 2005
    Publication date: December 1, 2005
    Inventors: Bih-Huey Lee, Hong-Yuan Chu, Ping-Kun Wu, Ching-Wen Lu, Jing-Cheng Lin, Shau-Lin Shue, Shing-Chyang Pan
  • Patent number: 6969912
    Abstract: An embedded microelectronic capacitor incorporating at least one ground shielding layer is provided which includes an upper ground shielding layer that has an aperture therethrough; an electrode plate positioned spaced-apart from the upper ground shielding layer that has a via extending upwardly away from the electrode plate through the aperture in the upper ground shielding layer providing electrical communication to the electrode plate without shorting to the upper ground shielding layer; a middle ground shielding layer positioned in the same plane of the electrode plate, surrounding while spaced-apart from the electrode plate at a predetermined distance; a lower ground shielding layer positioned spaced-apart from the electrode plate in an opposing relationship to the upper ground shielding layer; and a dielectric material embedding the upper ground shielding layer; the middle ground shielding layer and the lower ground shielding layer.
    Type: Grant
    Filed: November 14, 2003
    Date of Patent: November 29, 2005
    Assignee: Industrial Technology Research Institute
    Inventors: Uei-Ming Jow, Pei-Shen Wei, Ching-Liang Weng, Chun-Kun Wu, Chang-Sheng Chen, Ying-Jiunn Lai
  • Publication number: 20050216873
    Abstract: A sub-circuit based extraction method which extracts a multi-finger MOS transistor directly as a sub-circuit is described. By adding three marking layers, the method provides the layout extracted netlist with a complete list of device geometric parameters corresponding to the device properties as presented in the sub-circuit model based schematic netlist. By performing a layout-versus-schematic comparison based on all geometric parameters extracted, the layout checking is performed in a complete and accurate way where each device parameter is checked against the corresponding design schematic. This complete and accurate geometric parameter comparison enhances the confidence level of the layout physical verification.
    Type: Application
    Filed: March 23, 2004
    Publication date: September 29, 2005
    Inventors: Raminderpal Singh, Yue Tan, Jean-Oliver Plouchart, Lawrence Wagner, Mohamed Talbi, John Safran, Kun Wu
  • Publication number: 20050212956
    Abstract: The present invention measures a variability of a light source according to the relationship of the different brightness at different time points, to determine whether the light source has a periodic brightness. A suitable exposure time can be determined in accordance with the determined result that if the variability of a light source is within a tolerant range.
    Type: Application
    Filed: March 26, 2004
    Publication date: September 29, 2005
    Inventors: Ming-Kai Liao, Chung-Kun Wu
  • Publication number: 20050168913
    Abstract: The present invention describes an intermediate for use in a capacitive printed circuit board (PCB), which relates to a capacitive apparatus and manufacturing method for a built-in capacitor with a non-symmetrical electrode used to reduce inaccuracy of the error compression alignment on laminates. The invention employs a plurality of different sized metal laminates stacked for a built-in capacitor to achieve a high-precise capacitor PCB. More particularly, the invention can raise the capability of noise-immunity of a capacitive PCB applied to high frequency/speed modules and systems, and also provides precise capacitance to regular circuit design for the need of compact package and high-precise capacitance in the future.
    Type: Application
    Filed: July 21, 2004
    Publication date: August 4, 2005
    Inventors: Uei-Ming Jow, Ying-Jiunn Lai, Chun-Kun Wu, Pel-Shen Wei, Chang-Sheng Chen, Ching-Liang Weng
  • Publication number: 20050137220
    Abstract: A method is described for inhibiting mitogen activated protein kinase-activated protein kinase-2 in a subject in need of such inhibition, where the method involves administering to the subject a beta-carboline MK-2 inhibiting compound, or a pharmaceutically acceptable salt thereof.
    Type: Application
    Filed: July 20, 2004
    Publication date: June 23, 2005
    Applicant: Pharmacia Corporation
    Inventors: David Anderson, Ingrid Buchler, Shridhar Hegde, Matthew Mahoney, Marvin Meyers, David Reitz, John Trujillo, William Vernier, Kun Wu
  • Patent number: D518252
    Type: Grant
    Filed: June 7, 2004
    Date of Patent: March 28, 2006
    Inventor: Kuei-Kun Wu