Abstract: In certain aspects, a method for forming a three-dimensional (3D) memory device is disclosed. A first semiconductor structure including an array of NAND memory strings is formed on a first substrate. A second semiconductor structure including a recess gate transistor is formed on a second substrate. The recess gate transistor includes a recess gate structure protruding into the second substrate. The first semiconductor structure and the second semiconductor structure are bonded in a face-to-face manner, such that the array of NAND memory strings is coupled to the recess gate transistor across a bonding interface.

Abstract: Embodiments of three-dimensional memory devices and fabricating methods thereof are disclosed. One disclosed method for forming a memory structure comprises: forming a bottom conductive layer on a substrate; forming a dielectric stack on the bottom conductive layer, the dielectric stack comprising a plurality of alternatively arranged first dielectric layers and second dielectric layers; forming an opening penetrating the dielectric stack and exposing the bottom conductive layer; forming a cap layer on a bottom of the opening; forming a cylindrical body and a top contact on the cap layer and in the opening; and replacing the plurality of second dielectric layers with conductive layers.

Abstract: A method for data erasing of a non-volatile memory device is disclosed. The memory includes multiple memory cell strings each including a select gate transistor and multiple memory cells that are connected in series. The method comprises applying a step erase voltage to one memory cell string for an erase operation, the step erase voltage having a step-rising shaped voltage waveform. The method further comprises, during a period when the step erase voltage rises from an intermediate level to a peak level, raising a voltage of the select gate transistor from a starting level to a peak level, and raising a voltage of a predetermined region from a starting level to a peak level, such that a gate-induced drain leakage current is generated in the one memory cell string. The predetermined region is adjacent to the at least one select gate transistor and includes at least one memory cell.

Abstract: A three-dimensional (3D) memory device includes a first memory cell, a second memory cell, a control gate between the first and second memory cells, a top contact coupled to the first memory cell, and a bottom contact coupled to the second memory cell. The first memory cell can include a first pillar, a first insulating layer surrounding the first pillar, a first gate contact coupled to a first word line, and a second gate contact coupled to a first plate line. The second memory cell can include a second pillar, a second insulating layer surrounding the second pillar, a third gate contact coupled to a second word line, and a fourth gate contact coupled to a second plate line. The 3D memory device can utilize dynamic flash memory (DFM), increase storage density, provide multi-cell storage, provide a three-state logic, decrease leakage current, increase retention time, and decrease refresh rates.

Abstract: Three-dimensional (3D) memory devices and methods for forming the same are disclosed. In certain aspects, a 3D memory device includes a stack structure including interleaved conductive layers and stack dielectric layers, a channel structure extending through the stack structure, and a doped semiconductor layer. The channel structure includes a memory film and a semiconductor channel. The semiconductor channel includes a doped portion and an undoped portion. A part of the doped portion of the semiconductor channel extends beyond the stack structure in a first direction. A part of the doped semiconductor layer is in contact with a sidewall of the part of the doped portion of the semiconductor channel that extends beyond the stack structure.

Abstract: In an example, a method for forming a three-dimensional (3D) memory device is disclosed. A semiconductor layer is formed. A memory stack on the semiconductor is formed. A channel structure extending through the memory stack and the semiconductor layer is formed. An end of the channel structure abutting the semiconductor layer is exposed. A portion of the channel structure abutting the semiconductor layer is replaced with a semiconductor plug.

Abstract: A semiconductor device includes a first wafer, and a second wafer bonded with the first wafer and comprising a substrate and a device layer over the substrate. The first wafer is over the second wafer and includes memory arrays, array-base regions over the memory arrays, an isolation structure surrounding and insulating the array-base regions from one another, and bonding pads over the isolation structure. An array-base region of the array-base regions is connected with a memory array of the memory arrays. A bonding pad of the bonding pads is exposed.

Abstract: In certain aspects, a memory device includes a memory structure including memory strings, a first peripheral circuit coupled to the memory structure and including a first transistor including a first gate dielectric layer, a first semiconductor layer in contact with the first transistor, a second peripheral circuit coupled to the memory structure and including a second transistor including a second gate dielectric layer, and a second semiconductor layer in contact with the second transistor. The memory strings are between the first semiconductor layer and the second semiconductor layer in a first direction. A thickness of the first gate dielectric layer is greater than a thickness of the second gate dielectric layer in the first direction.

Abstract: A deep learning based method for integrating demand forecasting and scheduling of online ride-hailing at a hub is provided. The method includes: S1, performing data processing: performing missing value filling, outlier processing and normalization processing on the historical orders of online ride-hailing and relevant feature data of the urban transportation hub; S2, performing feature screening: primarily screening the relevant features by means of a Pearson correlation test and box plot analysis, calculating an influence degree of data of each feature on the orders of online ride-hailing by using an XGBoost algorithm, and secondarily screening the features; S3, performing model construction: constructing an integrated model for demand forecasting and scheduling decision of online ride-hailing at the urban transportation hub; and S4: performing algorithm design: designing a decision tree and deep learning combination algorithm, and calculating the number of online hailed rides to be scheduled.

Abstract: Embodiments of three-dimensional (3D) memory devices formed by bonded semiconductor devices and methods for forming the same are disclosed. In an example, a method for forming a semiconductor device is disclosed. The method includes the following operations. First, an insulating material layer can be formed over a substrate. In an example, single-crystalline silicon is not essential to the substrate. The insulating material layer can be patterned to form an isolation structure and a plurality of trenches in the isolation structure. A semiconductor material can be deposited to fill up the plurality of trenches to form a plurality of array-base regions in the isolation structure, the isolation structure insulating the plurality of array-base regions from one another. Further, a plurality of memory arrays can be formed over the plurality of array-base regions, and an insulating structure can be formed to cover the plurality of memory arrays and the plurality of array-base regions.

Abstract: This disclosure relates to mechanisms for allocating and mapping wireless communication resources for a multicast/broadcast session in a wireless network. In some exemplary implementations, data flows in a multicast/broadcast session may be duplicated and adaptively and dynamically mapped to multiple independent radio bearers, where each of these multiple independent radio beaters may be configured to either multicast the multicast/broadcast data to a group of target user equipments or unicast the multicast/broadcast data to a single user equipment.

Abstract: Provided is a system for monitoring a stage. The system comprises: a plurality of detection devices, a central control apparatus, and a presentation apparatus, wherein the plurality of detection devices are configured to detect environmental information of an environment where at least part of the stage apparatuses are located in real time, and to send the detected environmental information; the central control apparatus is connected to the at least part of the stage apparatuses and the presentation apparatus respectively, and configured to receive the environmental information, to acquire apparatus state information of at least one of the stage apparatuses and the detection devices, and to present the environmental information and the apparatus state information through the presentation apparatus.

Abstract: In an example, a three-dimensional (3D) memory device includes a stack structure including interleaved conductive layers and dielectric layers, a first semiconductor layer above the stack structure, a second semiconductor layer above the first semiconductor layer, channel structures extending vertically through the stack structure and the first semiconductor layer, and a source contact in contact with the second semiconductor layer.

Abstract: A method for data erasing of a non-volatile memory device is disclosed. The memory includes multiple memory cell strings each including a select gate transistor and multiple memory cells that are connected in series. The method comprises applying a step erase voltage to one memory cell string for an erase operation, the step erase voltage having a step-rising shaped voltage waveform. The method further comprises, during a period when the step erase voltage rises from an intermediate level to a peak level, raising a voltage of the select gate transistor from a starting level to a peak level, and raising a voltage of a predetermined region from a starting level to a peak level, such that a gate-induced drain leakage current is generated in the one memory cell string. The predetermined region is adjacent to the at least one select gate transistor and includes at least one memory cell.

Abstract: The present disclosure discloses a T-shaped three-level overload operating system, including a three-level topology and an overload mode switching system. The topology is connected with a first device group and a second device group which form a T shape; the first device group is designed with an overload capacity, and the second device group is designed with a rated capacity; and the overload mode switching system is configured for being connected to the topology to control the first device group to perform overload two-level operation on the topology, or to control the second device group to perform normal three-level operation on the topology, so that the number of device groups of the overload design can be effectively reduced, and then the cost of the system can be reduced. A working method of the T-shaped three-level overload operating system is further disclosed. The topology can be rapidly switched among working modes according to an output current of the topology.

Abstract: The present disclosure discloses a T-shaped three-level overload operating system, including a three-level topology and an overload mode switching system. The topology is connected with a first device group and a second device group which form a T shape; the first device group is designed with an overload capacity, and the second device group is designed with a rated capacity; and the overload mode switching system is configured for being connected to the topology to control the first device group to perform overload two-level operation on the topology, or to control the second device group to perform normal three-level operation on the topology, so that the number of device groups of the overload design can be effectively reduced, and then the cost of the system can be reduced. A working method of the T-shaped three-level overload operating system is further disclosed. The topology can be rapidly switched among working modes according to an output current of the topology.

Abstract: A surface-mounted polymer PTC overcurrent protection element having a small package size, comprising a PTC chip, an insulating layer (30), end electrodes (41, 42), and at least one conductive member (60). A dividing gap is designed on a first conductive electrode (21) to form first and second conductive areas (211, 212); the conductive member (60) is arranged at the edge or at least a corner of the first conductive area (211) side of the PTC chip, is used for conducting the first conductive area (211) and a second conductive electrode (22) on the PTC chip, and is not in contact with the end electrodes (41, 42); the main portion comprised in the dividing gap (70) of the first conductive electrode (21) is parallel to the longitudinal direction of the first end electrode (41) and the second end electrode (42). Also provided is a preparation method for the protection element. Thus, the miniaturized overcurrent protection element can satisfy the current PCB process to achieve requirements of mass production.