Patents by Inventor Kun-Yi Chou
Kun-Yi Chou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9245996Abstract: A LDMOS transistor device includes a substrate including a first insulating structure formed therein, a gate formed on the substrate and covering a portion of the first insulating structure, a drain region and a source region formed in the substrate at two respective sides of the gate, a base region encompassing the source region, and a doped layer formed under the base region. The drain region and the source region include a first conductivity type, the base region and the doped layer include a second conductivity type, and the second conductivity type is complementary to the first conductivity type. A top of the doped layer contacts a bottom of the base region. A width of the doped layer is larger than a width of the base region.Type: GrantFiled: January 2, 2014Date of Patent: January 26, 2016Assignee: UNITED MICROELECTRONICS CORP.Inventors: An-Hung Lin, Bo-Jui Huang, Kun-Yi Chou, Hsiao-Wen Liu, Kai-Cheng Chang
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Publication number: 20150187933Abstract: A LDMOS transistor device includes a substrate including a first insulating structure formed therein, a gate formed on the substrate and covering a portion of the first insulating structure, a drain region and a source region formed in the substrate at two respective sides of the gate, a base region encompassing the source region, and a doped layer formed under the base region. The drain region and the source region include a first conductivity type, the base region and the doped layer include a second conductivity type, and the second conductivity type is complementary to the first conductivity type. A top of the doped layer contacts a bottom of the base region. A width of the doped layer is larger than a width of the base region.Type: ApplicationFiled: January 2, 2014Publication date: July 2, 2015Applicant: UNITED MICROELECTRONICS CORP.Inventors: An-Hung Lin, Bo-Jui Huang, Kun-Yi Chou, Hsiao-Wen Liu, Kai-Cheng Chang
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Patent number: 8803235Abstract: A lateral-diffused metal oxide semiconductor device (LDMOS) includes a substrate, a first deep well, at least a field oxide layer, a gate, a second deep well, a first dopant region, a drain and a common source. The substrate has the first deep well which is of a first conductive type. The gate is disposed on the substrate and covers a portion of the field oxide layer. The second deep well having a second conductive type is disposed in the substrate and next to the first deep well. The first dopant region having a second conductive type is disposed in the second deep well. The doping concentration of the first dopant region is higher than the doping concentration of the second deep well.Type: GrantFiled: October 3, 2013Date of Patent: August 12, 2014Assignee: United Microelectronics Corp.Inventors: An-Hung Lin, Hong-Ze Lin, Bo-Jui Huang, Wei-Shan Liao, Ting-Zhou Yan, Kun-Yi Chou, Chun-Wei Chen
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Publication number: 20140035034Abstract: A lateral-diffused metal oxide semiconductor device (LDMOS) includes a substrate, a first deep well, at least a field oxide layer, a gate, a second deep well, a first dopant region, a drain and a common source. The substrate has the first deep well which is of a first conductive type. The gate is disposed on the substrate and covers a portion of the field oxide layer. The second deep well having a second conductive type is disposed in the substrate and next to the first deep well. The first dopant region having a second conductive type is disposed in the second deep well. The doping concentration of the first dopant region is higher than the doping concentration of the second deep well.Type: ApplicationFiled: October 3, 2013Publication date: February 6, 2014Applicant: UNITED MICROELECTRONICS CORP.Inventors: An-Hung Lin, Hong-Ze Lin, Bo-Jui Huang, Wei-Shan Liao, Ting-Zhou Yan, Kun-Yi Chou, Chun-Wei Chen
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Patent number: 8587058Abstract: The present invention provides a lateral diffused metal-oxide-semiconductor device including a first doped region, a second doped region, a third doped region, a gate structure, and a contact metal. The first doped region and the third doped region have a first conductive type, and the second doped region has a second conductive type. The second doped region, which has a racetrack-shaped layout, is disposed in the first doped region, and has a long axis. The third doped region is disposed in the second doped region. The gate structure is disposed on the first doped region and the second doped region at a side of the third doped region. The contact metal is disposed on the first doped region at a side of the second doped region extending out along the long axis, and is in contact with the first doped region.Type: GrantFiled: January 2, 2012Date of Patent: November 19, 2013Assignee: United Microelectronics Corp.Inventors: An-Hung Lin, Hong-Ze Lin, Bo-Jui Huang, Wei-Shan Liao, Ting-Zhou Yan, Kun-Yi Chou, Chun-Wei Chen, Ming-Yong Jian
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Patent number: 8581338Abstract: A lateral-diffused metal oxide semiconductor device (LDMOS) includes a substrate, a first deep well, at least a field oxide layer, a gate, a second deep well, a first dopant region, a drain and a common source. The substrate has the first deep well which is of a first conductive type. The gate is disposed on the substrate and covers a portion of the field oxide layer. The second deep well having a second conductive type is disposed in the substrate and next to the first deep well. The first dopant region having a second conductive type is disposed in the second deep well. The doping concentration of the first dopant region is higher than the doping concentration of the second deep well.Type: GrantFiled: May 12, 2011Date of Patent: November 12, 2013Assignee: United Microelectronics Corp.Inventors: An-Hung Lin, Hong-Ze Lin, Bo-Jui Huang, Wei-Shan Liao, Ting-Zhou Yan, Kun-Yi Chou, Chun-Wei Chen
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Patent number: 8482063Abstract: A high voltage semiconductor device is provided. A first-polarity buried layer is formed in the substrate. A first high voltage second-polarity well region is located over the first-polarity buried layer. A second-polarity base region is disposed within the first high voltage second-polarity well region. A source region is disposed within the second-polarity base region. A high voltage deep first-polarity well region is located over the first-polarity buried layer and closely around the first high voltage second-polarity well region. A first-polarity drift region is disposed within the high voltage deep first-polarity well region. A gate structure is disposed over the substrate. A second high voltage second-polarity well region is located over the first-polarity buried layer and closely around the high voltage deep first-polarity well region. A deep first-polarity well region is located over the first-polarity buried layer and closely around the second high voltage second-polarity well region.Type: GrantFiled: November 18, 2011Date of Patent: July 9, 2013Assignee: United Microelectronics CorporationInventors: An-Hung Lin, Hong-Ze Lin, Bo-Jui Huang, Wei-Shan Liao, Ting-Zhou Yan, Wei-Chun Chang, Chun-Yao Lee, Kun-Yi Chou
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Publication number: 20130168767Abstract: The present invention provides a lateral diffused metal-oxide-semiconductor device including a first doped region, a second doped region, a third doped region, a gate structure, and a contact metal. The first doped region and the third doped region have a first conductive type, and the second doped region has a second conductive type. The second doped region, which has a racetrack-shaped layout, is disposed in the first doped region, and has a long axis. The third doped region is disposed in the second doped region. The gate structure is disposed on the first doped region and the second doped region at a side of the third doped region. The contact metal is disposed on the first doped region at a side of the second doped region extending out along the long axis, and is in contact with the first doped region.Type: ApplicationFiled: January 2, 2012Publication date: July 4, 2013Inventors: An-Hung Lin, Hong-Ze Lin, Bo-Jui Huang, Wei-Shan Liao, Ting-Zhou Yan, Kun-Yi Chou, Chun-Wei Chen, Ming-Yong Jian
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Patent number: 8450801Abstract: A lateral-diffusion metal-oxide-semiconductor device includes a semiconductor substrate having at least a field oxide layer, a gate having a layout pattern of a racetrack shape formed on the substrate, a common source formed in the semiconductor substrate and enclosed by the gate, and a drain surrounding the gate and formed in the semiconductor substrate. The gate covers a portion of the field oxide layer. The common source includes a first doped region having a first conductive type and a plurality of islanding second doped regions having a second conductive type. The drain includes a third doped region having the first conductive type. The third doped region overlaps a portion of the field oxide layer and having an overlapping area between the third doped region and the field oxide layer.Type: GrantFiled: August 27, 2010Date of Patent: May 28, 2013Assignee: United Microelectronics Corp.Inventors: Hong-Ze Lin, Bo-Jui Huang, Chin-Lung Chen, Ting-Zhou Yan, Wei-Shan Liao, Han-Min Huang, Chun-Yao Lee, Kun-Yi Chou
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Publication number: 20130126968Abstract: A high voltage semiconductor device is provided. A first-polarity buried layer is formed in the substrate. A first high voltage second-polarity well region is located over the first-polarity buried layer. A second-polarity base region is disposed within the first high voltage second-polarity well region. A source region is disposed within the second-polarity base region. A high voltage deep first-polarity well region is located over the first-polarity buried layer and closely around the first high voltage second-polarity well region. A first-polarity drift region is disposed within the high voltage deep first-polarity well region. A gate structure is disposed over the substrate. A second high voltage second-polarity well region is located over the first-polarity buried layer and closely around the high voltage deep first-polarity well region. A deep first-polarity well region is located over the first-polarity buried layer and closely around the second high voltage second-polarity well region.Type: ApplicationFiled: November 18, 2011Publication date: May 23, 2013Applicant: UNITED MICROELECTRONICS CORPORATIONInventors: An-Hung LIN, Hong-Ze Lin, Bo-Jui Huang, Wei-Shan Liao, Ting-Zhou Yan, Wei-Chun Chang, Chun-Yao Lee, Kun-Yi Chou
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Publication number: 20120286359Abstract: A lateral-diffused metal oxide semiconductor device (LDMOS) includes a substrate, a first deep well, at least a field oxide layer, a gate, a second deep well, a first dopant region, a drain and a common source. The substrate has the first deep well which is of a first conductive type. The gate is disposed on the substrate and covers a portion of the field oxide layer. The second deep well having a second conductive type is disposed in the substrate and next to the first deep well. The first dopant region having a second conductive type is disposed in the second deep well. The doping concentration of the first dopant region is higher than the doping concentration of the second deep well.Type: ApplicationFiled: May 12, 2011Publication date: November 15, 2012Inventors: An-Hung Lin, Hong-Ze Lin, Bo-Jui Huang, Wei-Shan Liao, Ting-Zhou Yan, Kun-Yi Chou, Chun-Wei Chen
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Publication number: 20120049277Abstract: A lateral-diffusion metal-oxide-semiconductor device includes a semiconductor substrate having at least a field oxide layer, a gate having a layout pattern of a racetrack shape formed on the substrate, a common source formed in the semiconductor substrate and enclosed by the gate, and a drain surrounding the gate and formed in the semiconductor substrate. The gate covers a portion of the field oxide layer. The common source includes a first doped region having a first conductive type and a plurality of islanding second doped regions having a second conductive type. The drain includes a third doped region having the first conductive type. The third doped region overlaps a portion of the field oxide layer and having an overlapping area between the third doped region and the field oxide layer.Type: ApplicationFiled: August 27, 2010Publication date: March 1, 2012Inventors: Hong-Ze Lin, Bo-Jui Huang, Chin-Lung Chen, Ting-Zhou Yan, Wei-Shan Liao, Han-Min Huang, Chun-Yao Lee, Kun-Yi Chou