Abstract: A method for forming large substantially defect-free void areas on a semiconductor integrated circuit chip includes processing the chip through the passivation level processing operations then forming one or more openings in a designated blank area of the integrated circuit chip in a separate dedicated etching operation. The one or more openings may constitute 5-10% or more of the total area of the semiconductor chip. The void areas are deep trench openings that extend through the passivation layer and through all of the other material layers in the blank area exposing the substrate surface in one embodiment and through all material layers except for a field oxide layer formed directly on the substrate in another embodiment.

Abstract: A method for forming large substantially defect-free void areas on a semiconductor integrated circuit chip includes processing the chip through the passivation level processing operations then forming one or more openings in a designated blank area of the integrated circuit chip in a separate dedicated etching operation. The one or more openings may constitute 5-10% or more of the total area of the semiconductor chip. The void areas are deep trench openings that extend through the passivation layer and through all of the other material layers in the blank area exposing the substrate surface in one embodiment and through all material layers except for a field oxide layer formed directly on the substrate in another embodiment.

Abstract: An optical lithography exposure apparatus which may be a stepper or a scanner, provides a wafer chuck that retains a wafer and at least one opaque exposure shield that extends over a discrete peripheral edge portion of the wafer thereby preventing illumination from exposing the portion of the wafer beneath the exposure shield. In a positive photoresist system, the portions of the wafer blocked from exposure by the shields, include alignment marks and the unexposed photoresist remains over the alignment marks thereby protecting the alignment marks from destruction or damage during subsequent patterning operations used to form patterns in the film being patterned.

Abstract: A method and a computer readable medium includes instructions for obtaining time data as programmed into processing recipes or as recorded when a wafer is processed and transferred during lithography operations. The data is parsed and saved into an MES database. A report server accesses the database responsive to a query made of the database. A query may specify one or more fabrication parameters. The specified fabrication parameter or parameters is fixed and a data display is provided that compares times for processing and transferring wafers in various lithography operations used in the production of the semiconductor device and bottlenecks in lithography operations are identified by the comparative data.

Abstract: An optical lithography exposure apparatus which may be a stepper or a scanner, provides a wafer chuck that retains a wafer and at least one opaque exposure shield that extends over a discrete peripheral edge portion of the wafer thereby preventing illumination from exposing the portion of the wafer beneath the exposure shield. In a positive photoresist system, the portions of the wafer blocked from exposure by the shields, include alignment marks and the unexposed photoresist remains over the alignment marks thereby protecting the alignment marks from destruction or damage during subsequent patterning operations used to form patterns in the film being patterned.

Abstract: A method and a computer readable medium includes instructions for obtaining time data as programmed into processing recipes or as recorded when a wafer is processed and transferred during lithography operations. The data is parsed and saved into an MES database. A report server accesses the database responsive to a query made of the database. A query may specify one or more fabrication parameters. The specified fabrication parameter or parameters is fixed and a data display is provided that compares times for processing and transferring wafers in various lithography operations used in the production of the semiconductor device and bottlenecks in lithography operations are identified by the comparative data.

Abstract: A verification photomask disclosed. The mask may be for process window verification purposes when switching between fabrication equipment, and/or for optical proximity correction (OPC) verification purposes. The mask includes device areas that are separated by scribe lines. One or more verification patterns are integrated into the scribe lines for verification purposes. These patterns can include: proximity patterns, photoresist-spacing patterns, polysilicon end cap patterns, as well as other patterns. A method for making the mask, and a semiconductor device created at least in part by a method including use of the mask, are also disclosed.

Abstract: This invention relates to a method of fabrication used for semiconductor integrated circuit devices, and more specifically, to improve the photolithography processing window of a multi-layered dual damascene process by using a dielectric anti-reflective coating, DARC, comprised of multiple layers of silicon oxynitride, SiON, with varying k, dielectric constant values and thickness, to reduce reflectivity and improve light absorption. By varying both the thickness and the dielectric constant of the layers, the optical properties of light absorption, refractive indices, and light reflection are optimized.

Abstract: A new method is provided for the use of alignment marks. In prior art methods, a combination mask is mounted in a mask holder. The combination mask contains multiple, different alignment marks for different purposes and steps in a semiconductor processing sequence. This mark is printed onto the surface of a wafer. Using the method of the invention, a reticle is used that does not contain any patterns (a zero-layer reticle), on this zero-layer reticle an alignment mark is created. This zero-layer alignment mark is referred to as the zero-mark alignment mark, this alignment mark can be printed directly onto the wafer surface. Under the invention, the zero-layer reticle takes the place of the prior art mask holder, on the zero-layer reticle an alignment mark is created that can be directly printed from the zero-layer reticle onto the surface of a wafer. The zero-layer reticle further contains a multiplicity of production alignment marks in a location that is fixed with respect to the alignment mark.

Abstract: An optical proximity correction (OPC) verification mask is disclosed. The mask includes device areas that are separated by scribe lines. One or more OPC test patterns are integrated into the scribe lines for verification purposes. These patterns can include: line-end shortening (LES) patterns, such as serifs and hammerheads added to the ends of lines; corner rounding patterns, such as positive and negative serifs; and, scattering bars (SB's) and anti-scattering bars (ASB's) to compensate for isolated-dense proximity effects and isolated-feature depth of focus reduction. Other OPC patterns may also be included. A method for making the mask, and a semiconductor device created at least in part by a method including use of the mask, are also disclosed.

Abstract: A verification photomask disclosed. The mask may be for process window verification purposes when switching between fabrication equipment, and/or for optical proximity correction (OPC) verification purposes. The mask includes device areas that are separated by scribe lines. One or more verification patterns are integrated into the scribe lines for verification purposes. These patterns can include: proximity patterns, photoresist-spacing patterns, polysilicon end cap patterns, as well as other patterns. A method for making the mask, and a semiconductor device created at least in part by a method including use of the mask, are also disclosed.

Abstract: An optical proximity correction (OPC) verification mask is disclosed. The mask includes device areas that are separated by scribe lines. One or more OPC test patterns are integrated into the scribe lines for verification purposes. These patterns can include: line-end shortening (LES) patterns, such as serifs and hammerheads added to the ends of lines; corner rounding patterns, such as positive and negative serifs; and, scattering bars (SB's) and anti-scattering bars (ASB's) to compensate for isolated-dense proximity effects and isolated-feature depth of focus reduction. Other OPC patterns may also be included. A method for making the mask, and a semiconductor device created at least in part by a method including use of the mask, are also disclosed.

Abstract: During the course of manufacturing an IC, the thickness of the photoresist layer varies. In the presence of multiple steps, the difference between the maximum photoresist thickness and the minimum thickness can be quite substantial. It is sometimes the case that the minimum thickness is insufficient in some spots for proper exposure of the resist to be possible. The presence of such spots is detected by means of a monitor in the form of an optical mask comprising a group of lines whose width is close to the critical dimension together with an isolated line of similar width and a second, wider, isolated line. A photoresist image of the process monitor is formed in the kerf for each of the layers that is deposited, with the mask being shifted by about half its length between successive depositions. This ensures that a step is formed between successive layers so that if the photoresist layer is too thin at some point this will be reflected in the monitor.