Patents by Inventor Kun-Yi Wu
Kun-Yi Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240128876Abstract: A switching control circuit for use in controlling a resonant flyback power converter generates a first driving signal and a second driving signal. The first driving signal is configured to turn on the first transistor to generate a first current to magnetize a transformer and charge a resonant capacitor. The transformer and charge a resonant capacitor are connected in series. The second driving signal is configured to turn on the second transistor to generate a second current to discharge the resonant capacitor. During a power-on period of the resonant flyback power converter, the second driving signal includes a plurality of short-pulses configured to turn on the second transistor for discharging the resonant capacitor. A pulse-width of the short-pulses of the second driving signal is short to an extent that the second current does not exceed a current limit threshold.Type: ApplicationFiled: June 15, 2023Publication date: April 18, 2024Inventors: Yu-Chang Chen, Ta-Yung Yang, Kun-Yu Lin, Fu-Ciao Syu, Chia-Hsien Yang, Hsin-Yi Wu
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Publication number: 20240120844Abstract: A resonant flyback power converter includes: a first and a second transistors which form a half-bridge circuit for switching a transformer and a resonant capacitor to generate an output voltage; a current-sense device for sensing a switching current of the half-bridge circuit to generate a current-sense signal; and a switching control circuit generating a first and a second driving signals for controlling the first and the second transistors. The turn-on of the first driving signal controls the half-bridge circuit to generate a positive current to magnetize the transformer and charge the resonant capacitor. The turn-on of the second driving signal controls the half-bridge circuit to generate a negative current to discharge the resonant capacitor. The switching control circuit turns off the first transistor when the positive current exceeds a positive-over-current threshold, and/or, turns off the second transistor when the negative current exceeds a negative-over-current threshold.Type: ApplicationFiled: April 10, 2023Publication date: April 11, 2024Inventors: Kun-Yu LIN, Ta-Yung YANG, Yu-Chang CHEN, Hsin-Yi WU, Fu-Ciao SYU, Chia-Hsien YANG
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Publication number: 20240120845Abstract: A resonant flyback power converter includes: a first transistor and a second transistor which are configured to switch a transformer and a resonant capacitor for generating an output voltage; and a switching control circuit generating first and second driving signals for controlling the first and the second transistors. The turn-on of the first driving signal magnetizes the transformer. The second driving signal includes a resonant pulse having a resonant pulse width and a ZVS pulse during the DCM operation. The resonant pulse is configured to demagnetize the transformer. The resonant pulse has a first minimum resonant period for a first level of the output load and a second minimum resonant period for a second level of the output load. The first level is higher than the second level and the second minimum resonant period is shorter than the first minimum resonant period.Type: ApplicationFiled: April 14, 2023Publication date: April 11, 2024Inventors: Yu-Chang Chen, Ta-Yung Yang, Kun-Yu Lin, Hsin-Yi Wu
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Publication number: 20240120846Abstract: A resonant flyback power converter includes: a first transistor and a second transistor which are configured to switch a transformer and a resonant capacitor for generating an output voltage; and a switching control circuit generating first and second driving signals for controlling the first and the second transistors. The turn-on of the first driving signal magnetizes the transformer. During a DCM (discontinuous conduction mode) operation, the second driving signal includes a resonant pulse for demagnetizing the transformer and a ZVS (zero voltage switching) pulse for achieving ZVS of the first transistor. The resonant pulse is skipped when the output voltage is lower than a low-voltage threshold.Type: ApplicationFiled: April 14, 2023Publication date: April 11, 2024Inventors: Yu-Chang Chen, Ta-Yung Yang, Kun-Yu Lin, Hsin-Yi Wu
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Publication number: 20240078345Abstract: A method for tamper protection in cryptographic calculations is provided. A cryptographic calculation includes a plurality of normal rounds and a plurality of redundant rounds. The method includes obtaining a first variable x and a second variable y using a random number generator; dividing the normal rounds into a first normal section and a second normal section, and dividing the redundant rounds into a first redundant section and a second redundant section according to the first variable x and the second variable y; executing the first normal section and the first redundant section in sequence using a clock signal; in response to completion of the first redundant section and a first calculation result of the first normal section and a second calculation result of the first redundant section being the same, executing the second normal section and the second redundant section in sequence to complete the cryptographic calculation.Type: ApplicationFiled: September 5, 2023Publication date: March 7, 2024Inventors: Kun-Yi WU, Yu-Shan LI
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Publication number: 20240007283Abstract: A cryptographic device for a memory device includes a determination unit, a mapping unit, and a cryptographic unit. The determination unit determines that a memory address is in a protection area to select a key and a random number. The mapping unit maps a binary code to an injection code according to the key and the memory address, in which the binary code includes the random number and the memory address. The cryptographic unit generates a key stream according to the key and the injection code.Type: ApplicationFiled: May 30, 2023Publication date: January 4, 2024Inventors: Shun-Hsiung CHEN, Kun-Yi WU, Yu-Shan LI
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Publication number: 20230327867Abstract: An encryption device is provided, which includes a controller, a random controller, a first functional unit, and a second functional unit. The controller generates a first enable signal and a second enable signal. When at least one of the first enable signal and the second enable signal is in a first logic level, the random controller generates a first random signal and a second random signal. The first functional unit performs the corresponding operation according to the first enable signal and the first random signal. The second functional unit performs the corresponding operation according to the second enable signal and the second random signal.Type: ApplicationFiled: November 9, 2022Publication date: October 12, 2023Inventors: Kun-Yi WU, Yu-Shan LI
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Publication number: 20230214189Abstract: A carry-lookahead adder is provided. A first mask unit performs first mask operation on first input data with the first mask value to obtain first masked data. A second mask unit performs second mask operation on second input data with the second mask value to obtain second masked data. A first XOR gate receives the first and second mask values to provide a variable value. A half adder receives the first and second masked data to generate a propagation value and an intermediate generation value. A third mask unit performs third mask operation on the propagation value with the third mask value to obtain the third masked data. A carry-lookahead generator provides the carry output and the carry value according to carry input, the generation value, and the propagation value. The second XOR gate receives the third masked data and the carry value to provide the sum output.Type: ApplicationFiled: December 28, 2022Publication date: July 6, 2023Inventors: Kun-Yi WU, Yu-Shan LI
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Publication number: 20230214183Abstract: A carry-lookahead adder is provided. First XOR gate receives a first mask value and a second mask value to provide a variable. First mask unit performs a first mask operation on first input data with the variable to obtain first masked data. A half adder receives the first masked data and second input data to generate a propagation value and an intermediate generation value. Second mask unit performs a second mask operation on the propagation value with a third mask value to obtain second masked data. A logic circuit provides a generation value according to the propagation value, the intermediate generation value and the second mask value. A carry-lookahead generator provides a carry output and a carry value according to a carry input, the generation value and the propagation value. Second XOR gate receives the second masked data and the carry value to provide a sum output.Type: ApplicationFiled: December 28, 2022Publication date: July 6, 2023Inventors: Kun-Yi WU, Yu-Shan LI
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Publication number: 20230214216Abstract: An addition mask value generator is provided. A first operation circuit is configured to obtain first intermediate data according to first output mask value and fourth output mask value. A second operation circuit is configured to obtain the addition output mask value of a first mask group according to first intermediate data and fourth input mask value. A third operation circuit is configured to obtain second intermediate data according to second output mask value and third output mask value. A fourth operation circuit is configured to obtain the addition output mask value of a second mask group according to second intermediate data and second input mask value. The first and second addition input mask values of first mask group are first and second input mask values. The first and second addition input mask values of second mask group are third input mask value and first intermediate data.Type: ApplicationFiled: December 29, 2022Publication date: July 6, 2023Inventors: Kun-Yi WU, Yu-Shan LI
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Publication number: 20230216677Abstract: A cipher accelerator is provided. An encryption and decryption circuit is configured to perform an encryption and decryption operation according to a control signal. The encryption and decryption operation includes a plurality of normal rounds and a plurality of redundant rounds. A controller is configured to provide a control signal to the encryption and decryption circuit according to a first variable value and a second variable value. The encryption and decryption circuit is configured to divide the normal rounds into a first normal section and a second normal section according to the first variable value, and divide the redundant rounds into a first redundant section and a second redundant section according to the second variable value. The encryption and decryption circuit is configured to perform the first normal section, the first redundant section, the second normal section, and the second redundant section sequentially.Type: ApplicationFiled: November 9, 2022Publication date: July 6, 2023Inventors: Kun-Yi WU, Yu-Shan LI
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Publication number: 20230208821Abstract: A method for protecting and managing keys is provided. The method includes the following steps. An OTF cipher transmits a request message to a cryptographic engine to request that the cryptographic engine obtain a wrap key when a key is located in an external memory. The cryptographic engine requests the wrap key from a key store. The key store reads and transmits the wrap key to the cryptographic engine. The OTF cipher requests access to a protection key from the key store, and the key store requests that an external memory controller read the protection key from the external memory. The external memory transmits the protection key to the cryptographic engine. The cryptographic engine generates the key according to the wrap key and the protection key and transmits the key to the OTF cipher. The OTF cipher uses the key to perform an encryption and decryption process.Type: ApplicationFiled: December 20, 2022Publication date: June 29, 2023Inventors: Kun-Yi WU, Yu-Shan LI
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Patent number: 11494298Abstract: A one-time programmable memory device is provided in the invention. The one-time programmable memory device includes a one-time programmable memory and a memory controller. The one-time programmable memory includes a first block, a second block and a third block. The first block includes a plurality of initial-address-unit groups and each initial-address-unit group includes a plurality of initial address units and each initial address unit corresponds to a variable to record the storage address of its corresponding variable. The second block includes a plurality of initial address control units and each initial address control unit corresponds to one of the variables to record the corresponding initial-address-unit group of each variable. The third block includes a plurality of storage units and each storage unit has a corresponding storage address. The memory controller is configured to assign the storage addresses to the variables.Type: GrantFiled: October 1, 2020Date of Patent: November 8, 2022Assignee: NUVOTON TECHNOLOGY CORPORATIONInventors: Kun-Yi Wu, Yu-Shan Li
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Patent number: 11455401Abstract: A data-processing device is provided. The data-processing device includes: a flash memory, a computation unit, and a flash-memory controller. The flash-memory controller is electrically connected to the computation unit, and configured to control access to the flash memory. The flash-memory controller allocates a first execute-only memory (XOM) setting and a second XOM setting in a first memory bank and a second memory bank of the flash memory, respectively. The flash-memory controller allocates one or more XOM spaces in the flash memory according to the first XOM setting or the second XOM setting.Type: GrantFiled: May 30, 2019Date of Patent: September 27, 2022Assignee: NUVOTON TECHNOLOGY CORPORATIONInventors: Ming-Ying Liu, Kun-Yi Wu, Chun-Chi Chen
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Patent number: 11397535Abstract: A one-time programmable memory device is provided in the invention. The one-time programmable memory device includes a one-time programmable memory and a memory controller. The one-time programmable memory includes a first block and a second block. The first block includes a plurality of initial address units and each initial address unit corresponds to a variable to record the storage address of its corresponding variable, and wherein the second block includes a plurality of storage units and each storage unit has a corresponding storage address. The memory controller is coupled to the one-time programmable memory. The memory controller allocates the storage address to the variable. The content of each variable is stored in the storage unit corresponding to the storage address corresponding to the variable. The number of initial address units is smaller than the number of storage units.Type: GrantFiled: September 8, 2020Date of Patent: July 26, 2022Assignee: NUVOTON TECHNOLOGY CORPORATIONInventors: Kun-Yi Wu, Yu-Shan Li
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Publication number: 20210200440Abstract: A one-time programmable memory device is provided in the invention. The one-time programmable memory device includes a one-time programmable memory and a memory controller. The one-time programmable memory includes a first block and a second block. The first block includes a plurality of initial address units and each initial address unit corresponds to a variable to record the storage address of its corresponding variable, and wherein the second block includes a plurality of storage units and each storage unit has a corresponding storage address. The memory controller is coupled to the one-time programmable memory. The memory controller allocates the storage address to the variable. The content of each variable is stored in the storage unit corresponding to the storage address corresponding to the variable. The number of initial address units is smaller than the number of storage units.Type: ApplicationFiled: September 8, 2020Publication date: July 1, 2021Inventors: Kun-Yi WU, Yu-Shan LI
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Publication number: 20210200671Abstract: A one-time programmable memory device is provided in the invention. The one-time programmable memory device includes a one-time programmable memory and a memory controller. The one-time programmable memory includes a first block, a second block and a third block. The first block includes a plurality of initial-address-unit groups and each initial-address-unit group includes a plurality of initial address units and each initial address unit corresponds to a variable to record the storage address of its corresponding variable. The second block includes a plurality of initial address control units and each initial address control unit corresponds to one of the variables to record the corresponding initial-address-unit group of each variable. The third block includes a plurality of storage units and each storage unit has a corresponding storage address. The memory controller is configured to assign the storage addresses to the variables.Type: ApplicationFiled: October 1, 2020Publication date: July 1, 2021Inventors: Kun-Yi WU, Yu-Shan LI
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Publication number: 20200089894Abstract: A data-processing device is provided. The data-processing device includes: a flash memory, a computation unit, and a flash-memory controller. The flash-memory controller is electrically connected to the computation unit, and configured to control access to the flash memory. The flash-memory controller allocates a first execute-only memory (XOM) setting and a second XOM setting in a first memory bank and a second memory bank of the flash memory, respectively. The flash-memory controller allocates one or more XOM spaces in the flash memory according to the first XOM setting or the second XOM setting.Type: ApplicationFiled: May 30, 2019Publication date: March 19, 2020Inventors: Ming-Ying LIU, Kun-Yi WU, Chun-Chi CHEN
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Patent number: 9452316Abstract: A wheel chair includes two pedals, two transmission devices, two clutch members and two control units. Each transmission device includes a driving unit, a clutch unit and a rear wheel driving unit. Each of the clutch units includes an intermediate disk and a clutch disk which is co-rotatably connected with the intermediate disk. Each of the rear wheel driving units is connected between the rear wheel and the intermediate disk. Each clutch device includes a shifter which controls the clutch disk to be disengaged from the intermediate disk. The control units each control the clutch disk to be engaged with the intermediate disk so as to connect the rear wheels with the force from the driving units so as to rotate the patient's legs counter clockwise.Type: GrantFiled: October 27, 2014Date of Patent: September 27, 2016Inventor: Kun-Yi Wu
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Publication number: 20150141212Abstract: A wheel chair includes two pedals, two transmission devices, two clutch members and two control units. Each transmission device includes a driving unit, a clutch unit and a rear wheel driving unit. Each of the clutch units includes an intermediate disk and a driving disk which is co-rotatably connected with the intermediate disk. Each of the rear wheel driving units is connected between the rear wheel and the intermediate disk. Each clutch device includes a shifter which controls the clutch disk to be disengaged from the intermediate disk. The control units each control the clutch disk to be engaged with the intermediate disk so as to connect the rear wheels with the force from the driving units so as to rotate the patient's legs counter clockwise.Type: ApplicationFiled: October 27, 2014Publication date: May 21, 2015Inventor: Kun-Yi Wu