Abstract: A method for analyzing a specification parameter of an electronic component includes inputting a package type and at least one engineering drawing image of an electronic component; acquiring a probability value that in each view of the different viewing directions each of the plurality of specification parameter of the electronic component is labeled; taking the view of each of the plurality of specification parameters in the view direction with a highest probability value as a recommended view; performing a box selection on the plurality of specification parameters for at least one engineering drawing image with the same viewing direction as that of the recommended view by an object detection model; and identifying box-selected specification parameters to acquire a size value of identified specification parameters from the at least one engineering drawing image, and converting the size value into a corresponding editable text for output.

Abstract: An electronic component footprint setup system in collaboration with a circuit layout system and a method thereof are provided in the present disclosure. The electronic component footprint setup system in collaboration with a circuit layout system provides a user operating the circuit layout system with an interface on which parameters of an electronic component footprint to be created are configured; the parameters of the electronic component footprint are transformed for conforming to electronic component footprint specifications used in the circuit layout system; characteristic values of the electronic component footprint are calculated according to electronic component footprint specifications and electronic component footprint setup regulations; the electronic component footprint is created in the circuit layout system according to the characteristic values.

Abstract: A gate bias circuit for a plurality of GaAs amplifier stages is a transistor coupled to a temperature compensation current received from a CMOS control stage. A plurality of pHEMPT amplifier stages are coupled to the gate bias circuit and to a control voltage which switches the amplifier stage. A selectively controlled stage pass transistor enables a current mirror between the gate bias circuit and each stage amplifying transistor. The penultimate pHEMPT amplifier stage is coupled to a CMOS amplifier. A CMOS circuit provides both the temperature compensation current by a proportional to absolute temperature (PTAT) circuit and the control voltage enabling each pHEMPT transistor to receive its input signal in combination with the gate bias voltage.

Abstract: An electronic component footprint setup system in collaboration with a circuit layout system and a method thereof are provided in the present disclosure. The electronic component footprint setup system in collaboration with a circuit layout system provides a user operating the circuit layout system with an interface on which parameters of an electronic component footprint to be created are configured; the parameters of the electronic component footprint are transformed for conforming to electronic component footprint specifications used in the circuit layout system; characteristic values of the electronic component footprint are calculated according to electronic component footprint specifications and electronic component footprint setup regulations; the electronic component footprint is created in the circuit layout system according to the characteristic values.

Abstract: A gate bias circuit for a plurality of GaAs amplifier stages is a transistor coupled to a temperature compensation current received from a CMOS control stage. A plurality of pHEMPT amplifier stages are coupled to the gate bias circuit and to a control voltage which switches the amplifier stage. A selectively controlled stage pass transistor enables a current mirror between the gate bias circuit and each stage amplifying transistor. The penultimate pHEMPT amplifier stage is coupled to a CMOS amplifier. A CMOS circuit provides both the temperature compensation current by a proportional to absolute temperature (PTAT) circuit and the control voltage enabling each pHEMPT transistor to receive its input signal in combination with the gate bias voltage.

Abstract: A gate bias circuit for a plurality of GaAs amplifier stages is a transistor coupled to a temperature compensation current received from a CMOS control stage. A plurality of pHEMPT amplifier stages are coupled to the gate bias circuit and to a control voltage which switches the amplifier stage. A selectively controlled stage pass transistor enables a current mirror between the gate bias circuit and each stage amplifying transistor. The penultimate pHEMPT amplifier stage is coupled to a CMOS amplifier. A CMOS circuit provides both the temperature compensation current by a proportional to absolute temperature (PTAT) circuit and the control voltage enabling each pHEMPT transistor to receive its input signal in combination with the gate bias voltage.

Abstract: A gate bias circuit for a plurality of GaAs amplifier stages is a transistor coupled to a temperature compensation current received from a CMOS control stage. A plurality of pHEMPT amplifier stages are coupled to the gate bias circuit and to a control voltage which switches the amplifier stage. A selectively controlled stage pass transistor enables a current mirror between the gate bias circuit and each stage amplifying transistor. The penultimate pHEMPT amplifier stage is coupled to a CMOS amplifier. A CMOS circuit provides both the temperature compensation current by a proportional to absolute temperature (PTAT) circuit and the control voltage enabling each pHEMPT transistor to receive its input signal in combination with the gate bias voltage.

Abstract: A gate bias circuit for a plurality of GaAs amplifier stages is a transistor coupled to a temperature compensation current received from a CMOS control stage. A plurality of pHEMPT amplifier stages are coupled to the gate bias circuit and to a control voltage which switches the amplifier stage. A selectively controlled stage pass transistor enables a current mirror between the gate bias circuit and each stage amplifying transistor. The penultimate pHEMPT amplifier stage is coupled to a CMOS amplifier. A CMOS circuit provides both the temperature compensation current by a proportional to absolute temperature (PTAT) circuit and the control voltage enabling each pHEMPT transistor to receive its input signal in combination with the gate bias voltage.

Abstract: The present invention provides a millimeter-wave passive FET switch by using impedance transformation network to transfer the effective capacitance seen from the drain to source of an FET at off-state to low impedance, while transfer low impedance seen at on-state to high impedance. Since both on-state and off-state are transferred to high impedance, and low impedance respectively, a high-performance switch can be achieved. Since the size of the transformation network is small, the performance of the switch can be promoted with low cost.

Abstract: The present invention provides a millimeter-wave passive FET switch by using impedance transformation network to transfer the effective capacitance seen from the drain to source of an FET at off-state to low impedance, while transfer low impedance seen at on-state to high impedance. Since both on-state and off-state are transferred to high impedance, and low impedance respectively, a high-performance switch can be achieved. Since the size of the transformation network is small, the performance of the switch can be promoted with low cost.