Abstract: An apparatus for display an active region having a plurality of light-emitting elements, a gate scanning driver operatively coupled to the active region and configured to stop a gate scanning signal to the plurality of light-emitting elements in a period, and a light emitting driver operatively coupled to the active region and configured to cause the plurality of light-emitting elements to emit light in the period.

Abstract: An apparatus for display an active region having a plurality of light-emitting elements, a gate scanning driver operatively coupled to the active region and configured to stop a gate scanning signal to the plurality of light-emitting elements in a period, and a light emitting driver operatively coupled to the active region and configured to cause the plurality of light-emitting elements to emit light in the period.

Abstract: A driving apparatus of a light emitting diode (LED) display device is provided. The driving apparatus includes a timing control circuit. The timing control circuit outputs a plurality of driving control signals to a gate driving circuit on an LED display panel of the LED display device. Wherein, the plurality of driving control signals includes a first driving control signal and a second driving control signal, and the pulse width of the first driving control signal in a first horizontal line period is different from the pulse width of a second driving control signal in a second horizontal line period preceding to the first horizontal line period.

Abstract: A driving apparatus of a light emitting diode (LED) display device is provided. The driving apparatus includes a timing control circuit. The timing control circuit outputs a plurality of driving control signals to a gate driving circuit on an LED display panel of the LED display device. Wherein, the plurality of driving control signals includes a first driving control signal and a second driving control signal, and the pulse width of the first driving control signal in a first horizontal line period is different from the pulse width of a second driving control signal in a second horizontal line period preceding to the first horizontal line period.

Abstract: A driving apparatus of a light emitting diode (LED) display device is provided. The driving apparatus includes a timing control circuit. The timing control circuit outputs a plurality of driving control signals to a gate driving circuit on an LED display panel of the LED display device. Wherein, the plurality of driving control signals includes a first driving control signal and a second driving control signal, and the pulse width of the first driving control signal in a first horizontal line period is different from the pulse width of a second driving control signal in a second horizontal line period preceding to the first horizontal line period.

Abstract: A driving apparatus of a light emitting diode (LED) display device is provided. The driving apparatus includes a timing control circuit. The timing control circuit outputs a plurality of driving control signals to a gate driving circuit on an LED display panel of the LED display device. Wherein, the plurality of driving control signals includes a first driving control signal and a second driving control signal, and the pulse width of the first driving control signal in a first horizontal line period is different from the pulse width of a second driving control signal in a second horizontal line period preceding to the first horizontal line period.

Abstract: A display driving apparatus configured to drive a touch display panel is provided. The touch display panel includes gate drivers and scan lines. The display driving apparatus includes a driving controller. The driving controller provides clock signals to the gate drivers during a display period. The display period includes scan operation periods. The gate drivers drive the scan lines according to the clock signals during the scan operation periods. The driving controller further provides a clear signal and a pre-charge signal to at least one of the gate drivers to insert at least one touch sensing period between the scan operation periods, so that the touch display panel performs a touch sensing operation during the at least one touch sensing period. Furthermore, a method for driving the touch display panel is also provided.

Abstract: A display driving apparatus configured to drive a touch display panel is provided. The touch display panel includes gate drivers and scan lines. The display driving apparatus includes a driving controller. The driving controller provides clock signals to the gate drivers during a display period. The display period includes scan operation periods. The gate drivers drive the scan lines according to the clock signals during the scan operation periods. The driving controller further provides a clear signal and a pre-charge signal to at least one of the gate drivers to insert at least one touch sensing period between the scan operation periods, so that the touch display panel performs a touch sensing operation during the at least one touch sensing period. Furthermore, a method for driving the touch display panel is also provided.

Abstract: A method for use in a display panel is disclosed. The method includes providing M bus lines in the bus area for receiving a plurality of clock signals, M being a positive integer greater than 3; providing a plurality of signal lines to separately provide the clock signals from the M bus line to the circuit area, the circuit area configured to provide the plurality of sequential gate line signals in response to the clock signals, the plurality of signal lines including a plurality of adjacent signal-line pairs, each adjacent signal-line pair having a resistance difference, said signal lines including a maximum resistance value and a minimum resistance value, and wherein the M bus lines are arranged such that the resistance difference in any one of the adjacent signal-line pairs is smaller than a value difference between the maximum resistance value and the minimum resistance value.

Abstract: A display apparatus and a method for generating gate signal thereof are provided. The display apparatus includes a timing controller and a display panel. The timing controller is used for providing a plurality of timing signals. The display panel includes a pixel array and a gate drive circuit. The pixel array has a plurality of pixels. The gate drive circuit is electrically connected to the timing controller and the pixel array and including a plurality of shift register circuits. The shift register circuit includes a first shift register and a second shift register. The first shift register is configured for generating a corresponding primary gate signal. The second shift register is configured for generating a corresponding secondary gate signal. The timing controller adjusts overlapping relations of the timing signals according to a frame rate of the display apparatus.

Abstract: A display panel and its gate driving circuit are provided. The gate driving circuit includes a plurality of shift registers. Each of the shift registers includes a first scan signal generator for generating a first scan signal, a second scan signal generator for generating a second scan signal, a first control unit for generating a first control signal, and a second control unit for generating a second control signal. Here, the first control signal and the second control signal are shared by the first scan signal generator and the second scan signal generator. Based on the above, the abatement of signal intensity of the first scan signal and the second scan signal caused by circuit sharing can be precluded, and a chip area occupied by each of the shift registers can be reduced.

Abstract: A shift register circuit includes plural shift register stages for providing plural gate signals. Each shift register stage includes a pull-up unit, a pull-up control unit, an input unit, a first pull-down unit, a second pull-down unit, and a pull-down control unit. The pull-up control unit generates a first control signal according to a driving control voltage and a first clock. The pull-up unit pulls up a corresponding gate signal according to the first control signal. The input unit is utilized for inputting the gate signal of a preceding shift register stage to become the driving control voltage according to a second clock having a phase opposite to the first clock. The pull-down control unit generates a second control signal according to the driving control voltage. The first and second pull-down units pull down the corresponding gate signal and the first control signal respectively according to the second control signal.

Abstract: A LCD panel with an improved pixel array configuration is provided. The LCD panel uses a column inversion driving method to drive the data lines so as to achieve a stable common voltage. Moreover, by cross-connecting the layout traces of the wiring zone in a specified manner, the gate pulses outputted from every two gate lines neighboring the sub-pixel are not overlapped with each other, so that the frame can be normally displayed.

Abstract: A display apparatus and a method for generating gate signal thereof are provided. The display apparatus includes a timing controller and a display panel. The timing controller is used for providing a plurality of timing signals. The display panel includes a pixel array and a gate drive circuit. The pixel array has a plurality of pixels. The gate drive circuit is electrically connected to the timing controller and the pixel array and including a plurality of shift register circuits. The shift register circuit includes a first shift register and a second shift register. The first shift register is configured for generating a corresponding primary gate signal. The second shift register is configured for generating a corresponding secondary gate signal. The timing controller adjusts overlapping relations of the timing signals according to a frame rate of the display apparatus.

Abstract: A display panel is provided. A substrate includes a non-display area and a display area including a center area, a first area, and a second area. First data lines are disposed in the first area and electrically connected to the first source driving circuit. Second data lines are disposed in the second area and electrically connected to the second source driving circuit. At least one first repairing line is electrically connected to the first source driving circuit, passes through the center area of the display area and overlaps with the first data lines, wherein the first repairing line is electrically insulated from the first data lines. At least one second repairing line is electrically connected to the second source driving circuit, passes through the center area of the display area and overlaps with the second data lines, wherein the second repairing line is electrically insulated from the second data lines.

Abstract: A method for use in a display panel is disclosed. The method includes providing M bus lines in the bus area for receiving a plurality of clock signals, M being a positive integer greater than 3; providing a plurality of signal lines to separately provide the clock signals from the M bus line to the circuit area, the circuit area configured to provide the plurality of sequential gate line signals in response to the clock signals, the plurality of signal lines including a plurality of adjacent signal-line pairs, each adjacent signal-line pair having a resistance difference, said signal lines including a maximum resistance value and a minimum resistance value, and wherein the M bus lines are arranged such that the resistance difference in any one of the adjacent signal-line pairs is smaller than a value difference between the maximum resistance value and the minimum resistance value.

Abstract: A shift register circuit includes a plurality of shift registers. Each of the shift registers is configured for outputting a corresponding start-pulse signal and a corresponding driving-pulse signal. Each of the shift registers includes a pull-up circuit, a first driving circuit, a second driving circuit and a discharging circuit. The pull-up circuit is configured for charging a first node. The first driving circuit is configured for generating the corresponding start-pulse signal, and the second driving circuit is configured for generating the corresponding driving-pulse signal. The discharging circuit firstly discharges the first node before discharging an output terminal of the second driving circuit.

Abstract: A display panel and its gate driving circuit are provided. The gate driving circuit includes a plurality of shift registers. Each of the shift registers includes a first scan signal generator for generating a first scan signal, a second scan signal generator for generating a second scan signal, a first control unit for generating a first control signal, and a second control unit for generating a second control signal. Here, the first control signal and the second control signal are shared by the first scan signal generator and the second scan signal generator. Based on the above, the abatement of signal intensity of the first scan signal and the second scan signal caused by circuit sharing can be precluded, and a chip area occupied by each of the shift registers can be reduced.

Abstract: A pixel in a liquid crystal display panel comprises a first sub-pixel area having a first sub-pixel electrode and a second sub-pixel area having a second sub-pixel electrode. Each sub-pixel electrode is associated with a capacitor. When a gate-line signal and a data voltage is provided to the pixel, the voltage level on the first sub-pixel electrode is substantially equal to or slightly higher than the voltage level on the second sub-pixel electrode and the capacitor associated with each sub-pixel electrode is charged. When the gate-line signal has entirely passed on partially passed, a circuit element causes the capacitor associated with the second sub-pixel electrode to transfer its charge to another capacitor, resulting in a reduction of the voltage level on the second sub-pixel electrode.

Abstract: A shift register of an LCD device includes a plurality of shift register units coupled in series. Each shift register unit includes an input circuit and a pull-down circuit having symmetric structures which enable the LCD device to function in a forward-scan mode and a reverse-scan mode.