Abstract: A semiconductor packaging assembly includes a redistribution layered structure having a plurality of device regions and a plurality of cutting regions separating the device regions, a plurality of recess structures respectively formed in the cutting regions, a plurality of chips respectively disposed in the device regions, and an encapsulating layer formed on the redistribution layered structure to fill the recess structures and enclose the chips.

Abstract: A semiconductor package structure includes a first redistribution layer, a plurality of conductive connectors, a chip, and an encapsulant. The first redistribution layer has a first surface and a second surface opposite to the first surface. The first redistribution layer includes at least one conductive pattern and at least one dielectric layer stacked on each other. The conductive pattern includes a plurality of landing pads, and each of the landing pads is separated from the dielectric layer. The conductive connectors are located on the first surface. Each of the conductive connectors is corresponding to and electrically connected to one of the landing pads. The chip is located on the first surface. The chip is electrically connected to the first redistribution layer. The encapsulant encapsulates the chip and the conductive connectors. A manufacturing method of a semiconductor package structure is also provided.

Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a semiconductor die, an encapsulant, a redistribution layer, a polymer pattern and a heat dissipation structure. The semiconductor die has conductive pads at its active side, and is laterally encapsulated by the encapsulant. The redistribution layer is disposed at the active side of the semiconductor die, and spans over a front surface of the encapsulant. The redistribution layer is electrically connected with the conductive pads. The polymer pattern is disposed at a back surface of the encapsulant that is facing away from the front surface of the encapsulant. The semiconductor die is surrounded by the polymer pattern. The heat dissipation structure is in contact with a back side of the semiconductor die that is facing away from the active side, and extends onto the polymer pattern.

Abstract: A semiconductor package structure includes a first redistribution layer, a plurality of conductive connectors, a chip, and an encapsulant. The first redistribution layer has a first surface and a second surface opposite to the first surface. The first redistribution layer includes at least one conductive pattern and at least one dielectric layer stacked on each other. The conductive pattern includes a plurality of landing pads, and each of the landing pads is separated from the dielectric layer. The conductive connectors are located on the first surface. Each of the conductive connectors is corresponding to and electrically connected to one of the landing pads. The chip is located on the first surface. The chip is electrically connected to the first redistribution layer. The encapsulant encapsulates the chip and the conductive connectors. A manufacturing method of a semiconductor package structure is also provided.

Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a semiconductor die, an encapsulant, a redistribution layer, a polymer pattern and a heat dissipation structure. The semiconductor die has conductive pads at its active side, and is laterally encapsulated by the encapsulant. The redistribution layer is disposed at the active side of the semiconductor die, and spans over a front surface of the encapsulant. The redistribution layer is electrically connected with the conductive pads. The polymer pattern is disposed at a back surface of the encapsulant that is facing away from the front surface of the encapsulant. The semiconductor die is surrounded by the polymer pattern. The heat dissipation structure is in contact with a back side of the semiconductor die that is facing away from the active side, and extends onto the polymer pattern.

Abstract: A fan-out package with warpage reduction has a redistribution layer (RDL), at least one bare chip and a multi-layer encapsulation. A plurality of metal bumps on an active surface of each bare chip are respectively and electrically connected to a plurality of inner pads of the RDL. The multi-layer encapsulation is formed on the RDL to encapsulate the least one bare chip and at least has two different encapsulation layers with different coefficient of thermal expansions (CTE) to encapsulate different portions of sidewalls of each bare chip. One of the encapsulation layers with the smallest CTE is close to RDL. Therefore, in a step of forming the multi-layer encapsulation at high temperature, the suitable CTEs of the encapsulation layers are selected to reduce a warpage between the encapsulation layer and a material layer thereto.

Abstract: A manufacturing method of a redistribution layer is provided. The method includes the following steps. A patterned sacrificial layer is formed on a carrier. An actuate angle is formed between a side wall of the patterned sacrificial layer and the carrier. A first conductive layer is formed. The first conductive layer includes a plurality of first portions formed on the carrier and a plurality of second portions formed on the patterned sacrificial layer. The patterned sacrificial layer and the second portions of the first conductive layer are removed from the carrier. Another manufacturing method of a redistribution layer is also provided.

Abstract: A manufacturing method of a package structure is provided. The method includes the following steps. A semiconductor chip is bonded on a carrier, wherein the semiconductor chip comprises a plurality of conductive pads. An insulating material layer is formed over the carrier and encapsulating the semiconductor chip, wherein a thickness of the insulating material layer is greater than a thickness of the semiconductor chip. A first surface of the insulating material layer is patterned to form first openings that expose the conductive pads of the semiconductor chip, and second openings that penetrate through the insulating material layer. A plurality of conductive posts is formed in the first openings, wherein the plurality of conductive posts is electrically connected to the plurality of conductive pads of the semiconductor chip. A plurality of conductive vias is formed in the second opening.

Abstract: A manufacturing method of a package structure is provided. The method includes the following steps. A semiconductor chip is bonded on a carrier, wherein the semiconductor chip comprises a plurality of conductive pads. An insulating material layer is formed over the carrier and encapsulating the semiconductor chip, wherein a thickness of the insulating material layer is greater than a thickness of the semiconductor chip. A first surface of the insulating material layer is patterned to form first openings that expose the conductive pads of the semiconductor chip, and second openings that penetrate through the insulating material layer. A plurality of conductive posts is formed in the first openings, wherein the plurality of conductive posts is electrically connected to the plurality of conductive pads of the semiconductor chip. A plurality of conductive vias is formed in the second opening.

Abstract: A semiconductor package including a chip stack, at least one conductive wire, a first insulating encapsulant, a second insulating encapsulant, and a redistribution layer is provided, and a manufacturing method thereof is also provided. The chip stack includes semiconductor chips stacked on top of each other. Each semiconductor chip has an active surface that has at least one bonding region, and each bonding region is exposed by the chip stack. The conductive wire is correspondingly disposed on the bonding region. The first insulating encapsulant encapsulates the bonding region and the conductive wire. At least a portion of each conductive wire is exposed from the first insulating encapsulant. The second insulating encapsulant encapsulates the chip stack and the first insulating encapsulant. The first insulating encapsulant is exposed from the second insulating encapsulant. The redistribution layer is disposed on the first and second insulating encapsulant and electrically coupled to the conductive wire.

Abstract: An encapsulating composition and a semiconductor package are provided. The encapsulating composition adapted to encapsulate a semiconductor die includes a photosensitive dielectric material and a polarizable compound suspended in the photosensitive dielectric material. The polarizable compound within a predetermined region of the encapsulating composition affected by an external stimulus is arranged uniformly in a thickness direction to provide a conductive path penetrating through the photosensitive dielectric material along the thickness direction. The semiconductor package includes the encapsulating composition encapsulating the semiconductor die, a first and a second redistribution layer. The first and the second redistribution layer disposed on the opposite sides of the encapsulating composition are electrically connected each other through the encapsulating composition. A manufacturing method of the semiconductor package is also provided.

Abstract: A manufacturing method of a semiconductor package structure is provided. The method includes the following steps. A first redistribution layer is formed on a first surface of a semiconductor substrate. A plurality of through holes and an opening are formed on the semiconductor substrate. A chip is disposed in the opening of the semiconductor substrate. A conductive through via is formed in the through holes to electrically connect the first redistribution layer. A second redistribution layer is formed on a second surface of the semiconductor substrate opposite to the first surface to electrically connect the chip. The second redistribution layer is electrically connected to the first redistribution layer by the conductive through via. A plurality of conductive structures are formed on the second redistribution layer. A semiconductor package structure is also provided.

Abstract: A manufacturing method of a redistribution layer is provided. The method includes the following steps. A patterned sacrificial layer is formed on a carrier. An actuate angle is formed between a side wall of the patterned sacrificial layer and the carrier. A first conductive layer is formed. The first conductive layer includes a plurality of first portions formed on the carrier and a plurality of second portions formed on the patterned sacrificial layer. The patterned sacrificial layer and the second portions of the first conductive layer are removed from the carrier. Another manufacturing method of a redistribution layer is also provided.

Abstract: An image sensor including a device chip, a plurality of spacers, a dam layer, a lid, and a plurality of conductive terminals. The device chip has a first surface and a second surface opposite to the first surface. The device chip includes a sensing area on the first surface and a plurality of conductive pads surrounding the sensing area. The spacers are over the first surface of the device chip. The dam layer encapsulates the conductive pads and the spacers. The lid is over the dam layer. The conductive terminals are over the second surface of the device chip and are electrically connected to the conductive pads. In addition, a manufacturing method of the image sensor is also provided.

Abstract: A testing method for testing an integrated circuit device includes the steps of forming compliant bumps on bonding pads on a substrate of the device such that each of the compliant bumps has a polymeric body formed on a corresponding one of the bonding pads and a metal layer formed on the polymeric body, and such that the metal layer has a probe-contacting surface formed with a plurality of recesses, and testing electrical continuity between the metal layer of each of the compliant bumps and a corresponding circuit of the device by contacting a probe of a testing apparatus with the recessed probe-contacting surface of the metal layer.