Abstract: A single-ended signaling system in which transmitted and returned signal currents are enabled to flow substantially parallel to one another and thereby maintain a substantially uniform impedance along the length of a single-ended signal conductor. A reference plane is disposed substantially parallel to a single-ended signaling conductor and coupled to the signaling conductor within a signal-receiving IC and to signaling supply voltage nodes within a signal-transmitting IC. By this arrangement, an signal current flowing to or from the receiving IC via the signaling conductor is conducted to the reference plane, thereby enabling a signal-return current to flow back to or back from the transmitting IC along a single path that is substantially parallel to the signal conductor.

Abstract: A single-ended signaling system in which transmitted and returned signal currents are enabled to flow substantially parallel to one another and thereby maintain a substantially uniform impedance along the length of a single-ended signal conductor. A reference plane is disposed substantially parallel to a single-ended signaling conductor and coupled to the signaling conductor within a signal-receiving IC and to signaling supply voltage nodes within a signal-transmitting IC. By this arrangement, an signal current flowing to or from the receiving IC via the signaling conductor is conducted to the reference plane, thereby enabling a signal-return current to flow back to or back from the transmitting IC along a single path that is substantially parallel to the signal conductor.

Abstract: Transmit parallel interfaces and methods are provided in which a clock signal is generated that maximizes the setup and hold window of input data. In at least some embodiments, a divider circuit provides a clock signal in one clock domain that has a rising edge located very close to the falling edge of a system clock in another clock domain.

Abstract: Dual loop phase lock loops having a high loop bandwidth with low power consumption are described. Each loop is provided with a voltage supply regulator circuit which regulates the voltage of a portion of each loop. In one embodiment, the outer loop employs a regulation circuit comprising a two stage operational amplifier which is compensated by a compensation circuit that is configured to ensure that the dominant pole of the operational amplifier is associated with the first stage of the operational amplifier.

Abstract: Dual loop phase lock loops having a high loop bandwidth with low power consumption are described. Each loop is provided with a voltage supply regulator circuit which regulates the voltage of a portion of each loop. In one embodiment, the outer loop employs a regulation circuit comprising a two stage operational amplifier which is compensated by a compensation circuit that is configured to ensure that the dominant pole of the operational amplifier is associated with the first stage of the operational amplifier.

Abstract: Transmit parallel interfaces and methods are provided in which a clock signal is generated that maximizes the setup and hold window of input data. In at least some embodiments, a divider circuit provides a clock signal in one clock domain that has a rising edge located very close to the falling edge of a system clock in another clock domain.

Abstract: Dual loop phase lock loops having a high loop bandwidth with low power consumption are described. Each loop is provided with a voltage supply regulator circuit which regulates the voltage of a portion of each loop. In one embodiment, the outer loop employs a regulation circuit comprising a two stage operational amplifier which is compensated by a compensation circuit that is configured to ensure that the dominant pole of the operational amplifier is associated with the first stage of the operational amplifier.

Abstract: A clock generator generates a first clock signal and a second clock signal such that the timing of the first and second clock signals is adjustable. A phase detector is coupled to receive the first and second clock signals and generate a skip signal by integrating the first clock signal over one half of a clock cycle. The skip signal indicates whether the first clock signal is ahead of the second clock signal. The first and second clock signals are calibrated individually. The skip signal generated by the phase detector indicates whether a load pulse should be sampled.