Patents by Inventor Kunal A. Khochare
Kunal A. Khochare has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11404105Abstract: A write history buffer can prevent write disturb in memory, enabling a reduction in write disturb refresh rate and improvement in performance. A memory device can include circuitry to cause consecutive write commands to the same address to be spaced by an amount of time to reduce incidences of write disturb, and therefore reduce the required write disturb refresh rate and improve performance. In one example, a memory device receives multiple write commands to an address. In response to receipt of the multiple write commands, the first write command is sent to the memory and a timer is started. Subsequent write commands that are received after the first write command and before expiration of the timer are held in a buffer. After expiration of the timer, only the most recent of the subsequent write commands to the address is sent to the memory array.Type: GrantFiled: December 21, 2020Date of Patent: August 2, 2022Assignee: Intel CorporationInventors: Akanksha Mehta, Benjamin Graniello, Rakan Maddah, Philip Hillier, Richard P. Mangold, Prashant S. Damle, Kunal A. Khochare
-
Publication number: 20210110862Abstract: A write history buffer can prevent write disturb in memory, enabling a reduction in write disturb refresh rate and improvement in performance. A memory device can include circuitry to cause consecutive write commands to the same address to be spaced by an amount of time to reduce incidences of write disturb, and therefore reduce the required write disturb refresh rate and improve performance. In one example, a memory device receives multiple write commands to an address. In response to receipt of the multiple write commands, the first write command is sent to the memory and a timer is started. Subsequent write commands that are received after the first write command and before expiration of the timer are held in a buffer. After expiration of the timer, only the most recent of the subsequent write commands to the address is sent to the memory array.Type: ApplicationFiled: December 21, 2020Publication date: April 15, 2021Inventors: Akanksha MEHTA, Benjamin GRANIELLO, Rakan MADDAH, Philip HILLIER, Richard P. MANGOLD, Prashant S. DAMLE, Kunal A. KHOCHARE
-
Patent number: 10915254Abstract: Technologies for accessing memory devices of a memory module device includes receiving a memory read request form a host and reading, in response to the memory read request, a rank of active non-volatile memory devices of the memory module device while contemporaneously accessing a volatile memory device of the memory module device. The volatile memory device shares data lines of a data bus of the memory module device with a spare non-volatile memory device associated with the rank of active non-volatile memory devices. During write operations, each of the rank of active non-volatile memory devices and the spare non-volatile memory device associated with the rank of active non-volatile memory devices are written to facilitate proper wear leveling of the non-volatile memory devices. The spare non-volatile memory device may replace a failed non-volatile memory devices of the rank of active non-volatile memory devices.Type: GrantFiled: May 7, 2019Date of Patent: February 9, 2021Assignee: Intel CorporationInventors: Kunal A. Khochare, Camille C. Raad, Richard P. Mangold, Shachi K. Thakkar
-
Publication number: 20200133578Abstract: Technologies for issuing commands on selected memory devices includes an apparatus that includes a data storage controller and multiple non-volatile, write in place, byte or block addressable memory devices. The memory devices are arranged in one or more ranks, and the memory devices in each rank are connected to a same communication channel. The data storage controller is to select a subgroup of the plurality of the memory devices in a rank without modifying an identifier of each memory device, and issue a command to operate on data of the selected subgroup.Type: ApplicationFiled: October 29, 2019Publication date: April 30, 2020Inventors: Muthukumar P. Swaminathan, Kunal A. Khochare
-
Patent number: 10459659Abstract: Technologies for issuing commands on selected memory devices includes an apparatus that includes a data storage controller and multiple non-volatile, write in place, byte or block addressable memory devices. The memory devices are arranged in one or more ranks, and the memory devices in each rank are connected to a same communication channel. The data storage controller is to select a subgroup of the plurality of the memory devices in a rank without modifying an identifier of each memory device, and issue a command to operate on data of the selected subgroup.Type: GrantFiled: March 31, 2017Date of Patent: October 29, 2019Assignee: Intel CorporationInventors: Muthukumar P. Swaminathan, Kunal A. Khochare
-
Patent number: 10452312Abstract: Provided are an apparatus, system and method to determine whether to use a low or high read voltage. First level indications of write addresses, for locations in the non-volatile memory to which write requests have been directed, are included in a first level data structure. For a write address of the write addresses having a first level indication in the first level data structure, the first level indication of the write address is removed from the first level data structure and a second level indication for the write address is added to a second level data structure to free space in the first level data structure to indicate a further write address. A first voltage level is used to read data from read addresses mapping to one of the first and second level indications in the first and the second level data structures, respectively.Type: GrantFiled: December 30, 2016Date of Patent: October 22, 2019Assignee: INTEL CORPORATIONInventors: Zhe Wang, Zeshan A. Chishti, Muthukumar P. Swaminathan, Alaa R. Alameldeen, Kunal A. Khochare, Jason A. Gayman
-
Publication number: 20190258414Abstract: Technologies for accessing memory devices of a memory module device includes receiving a memory read request form a host and reading, in response to the memory read request, a rank of active non-volatile memory devices of the memory module device while contemporaneously accessing a volatile memory device of the memory module device. The volatile memory device shares data lines of a data bus of the memory module device with a spare non-volatile memory device associated with the rank of active non-volatile memory devices. During write operations, each of the rank of active non-volatile memory devices and the spare non-volatile memory device associated with the rank of active non-volatile memory devices are written to facilitate proper wear leveling of the non-volatile memory devices. The spare non-volatile memory device may replace a failed non-volatile memory devices of the rank of active non-volatile memory devices.Type: ApplicationFiled: May 7, 2019Publication date: August 22, 2019Inventors: Kunal A. Khochare, Camille C. Raad, Richard P. Mangold, Shachi K. Thakkar
-
Patent number: 10310989Abstract: One embodiment provides a memory controller. The memory controller includes a memory controller memory; a timestamp circuitry and a demarcation voltage (VDM) selection circuitry. The timestamp circuitry is to capture a current timer index from a timer circuitry in response to an initiation of a periodic patrol scrub and to compare the current timer index to a stored timestamp. The VDM selection circuitry is to update a state of a sub-block of a memory array, if the state is less than a threshold and a difference between the current timer index and the stored timestamp is nonzero. The timestamp circuitry is further to store the current timer index as a new timestamp.Type: GrantFiled: September 29, 2017Date of Patent: June 4, 2019Assignee: Intel CorporationInventors: Philip Hillier, Jeffrey W. Ryden, Muthukumar P. Swaminathan, Zion S. Kwok, Kunal A. Khochare, Richard P. Mangold, Prashant S. Damle
-
Patent number: 10296238Abstract: Technologies for accessing memory devices of a memory module device includes receiving a memory read request form a host and reading, in response to the memory read request, a rank of active non-volatile memory devices of the memory module device while contemporaneously accessing a volatile memory device of the memory module device. The volatile memory device shares data lines of a data bus of the memory module device with a spare non-volatile memory device associated with the rank of active non-volatile memory devices. During write operations, each of the rank of active non-volatile memory devices and the spare non-volatile memory device associated with the rank of active non-volatile memory devices are written to facilitate proper wear leveling of the non-volatile memory devices. The spare non-volatile memory device may replace a failed non-volatile memory devices of the rank of active non-volatile memory devices.Type: GrantFiled: December 18, 2015Date of Patent: May 21, 2019Assignee: Intel CorporationInventors: Kunal A. Khochare, Camille C. Raad, Richard P. Mangold, Shachi K. Thakkar
-
Publication number: 20190102320Abstract: One embodiment provides a memory controller. The memory controller includes a memory controller memory; a timestamp circuitry and a demarcation voltage (VDM) selection circuitry. The timestamp circuitry is to capture a current timer index from a timer circuitry in response to an initiation of a periodic patrol scrub and to compare the current timer index to a stored timestamp. The VDM selection circuitry is to update a state of a sub-block of a memory array, if the state is less than a threshold and a difference between the current timer index and the stored timestamp is nonzero. The timestamp circuitry is further to store the current timer index as a new timestamp.Type: ApplicationFiled: September 29, 2017Publication date: April 4, 2019Applicant: INTEL CORPORATIONInventors: Philip Hillier, Jeffrey W. Ryden, Muthukumar P. Swaminathan, Zion S. Kwok, Kunal A. Khochare, Richard P. Mangold, Prashant S. Damle
-
Publication number: 20180285020Abstract: Technologies for issuing commands on selected memory devices includes an apparatus that includes a data storage controller and multiple non-volatile, write in place, byte or block addressable memory devices. The memory devices are arranged in one or more ranks, and the memory devices in each rank are connected to a same communication channel. The data storage controller is to select a subgroup of the plurality of the memory devices in a rank without modifying an identifier of each memory device, and issue a command to operate on data of the selected subgroup.Type: ApplicationFiled: March 31, 2017Publication date: October 4, 2018Inventors: Muthukumar P. Swaminathan, Kunal A. Khochare
-
APPARATUS, SYSTEM AND METHOD TO DETERMINE A DEMARCATION VOLTAGE TO USE TO READ A NON-VOLATILE MEMORY
Publication number: 20180188953Abstract: Provided are an apparatus, system and method to determine whether to use a low or high read voltage. First level indications of write addresses, for locations in the non-volatile memory to which write requests have been directed, are included in a first level data structure. For a write address of the write addresses having a first level indication in the first level data structure, the first level indication of the write address is removed from the first level data structure and a second level indication for the write address is added to a second level data structure to free space in the first level data structure to indicate a further write address. A first voltage level is used to read data from read addresses mapping to one of the first and second level indications in the first and the second level data structures, respectively.Type: ApplicationFiled: December 30, 2016Publication date: July 5, 2018Inventors: Zhe WANG, Zeshan A. CHISHTI, Muthukumar P. SWAMINATHAN, Alaa R. ALAMELDEEN, Kunal A. KHOCHARE, Jason A. GAYMAN -
Patent number: 9934859Abstract: In response to a write operation on a storage element in a non-volatile memory device, a count provided by a global counter is stored to indicate a time at which the write operation occurs on the storage element. In response to receiving a request perform a read operation on the storage element, a determination is made of a demarcation voltage to apply for performing the read operation on the storage element, based on a progress of the global counter since the write operation on the storage element.Type: GrantFiled: December 27, 2016Date of Patent: April 3, 2018Assignee: INTEL CORPORATIONInventors: Muthukumar P. Swaminathan, Zion S. Kwok, Prashant S. Damle, Kunal A. Khochare, Philip Hillier, Jeffrey W. Ryden, Richard P. Mangold
-
Publication number: 20170177244Abstract: Technologies for accessing memory devices of a memory module device includes receiving a memory read request form a host and reading, in response to the memory read request, a rank of active non-volatile memory devices of the memory module device while contemporaneously accessing a volatile memory device of the memory module device. The volatile memory device shares data lines of a data bus of the memory module device with a spare non-volatile memory device associated with the rank of active non-volatile memory devices. During write operations, each of the rank of active non-volatile memory devices and the spare non-volatile memory device associated with the rank of active non-volatile memory devices are written to facilitate proper wear leveling of the non-volatile memory devices. The spare non-volatile memory device may replace a failed non-volatile memory devices of the rank of active non-volatile memory devices.Type: ApplicationFiled: December 18, 2015Publication date: June 22, 2017Inventors: Kunal A. Khochare, Camille C. Raad, Richard P. Mangold, Shachi K. Thakkar