Abstract: Stacked circuits are configured to facilitate post-stacking testing. According to one example, a stacked circuit may include a first die electrically coupled to a second die through a plurality of interconnects. The first die may include a test input interface configured to receive test data signals and a source test clock signal, a test output interface configured to convey test responses, a first test signal path, at least one first die-to-die output interface configured to convey to the second die the test data signals and a low-latency clock signal received from a low-latency clock path between the test input interface and the at least one first die-to-die output interface, and at least one first die-to-die input interface configured to receive test responses and the clock signal from the second die. Other aspects, embodiments, and features are also included.