Abstract: A method of forming an all solid-state thin-film battery that can be scaled down and be integrated into a CMOS process is provided. The method includes a lift-off process in which battery material layers formed upon a patterned sacrificial material are removed from a bottom electrode, while battery material layers that are formed directly on a surface of the bottom electrode remain after performing the lift-off process. In some embodiments, a solid-state lithium based battery can be formed that includes a thin lithiated cathode material layer (thickness of less than 200 nm) composed of LiCoO2. Such a solid-state lithium based battery exhibits enhanced battery performance in terms of charge rate and specific charge capacity.

Abstract: A method for reducing crystalline defects in a semiconductor structure is presented. The method includes epitaxially growing a first crystalline material over a crystalline substrate, epitaxially growing a second crystalline material over the first crystalline material, and patterning and removing portions of the second crystalline material to form openings. The method further includes converting the first crystalline material into a non-crystalline material, depositing a thermally stable material in the openings, depositing a capping layer over the second crystalline material and the thermally stable material to form a substantially enclosed semiconductor structure, and annealing the substantially enclosed semiconductor structure.

Abstract: A method for reducing crystalline defects in a semiconductor structure is presented. The method includes epitaxially growing a first crystalline material over a crystalline substrate, epitaxially growing a second crystalline material over the first crystalline material, and patterning and removing portions of the second crystalline material to form openings. The method further includes converting the first crystalline material into a non-crystalline material, depositing a thermally stable material in the openings, depositing a capping layer over the second crystalline material and the thermally stable material to form a substantially enclosed semiconductor structure, and annealing the substantially enclosed semiconductor structure.

Abstract: Provided is a light emitting semiconductor structure that operates as a light emitting diode (LED). In embodiments of the invention, the light emitting semiconductor structure includes a first barrier region, a second barrier region, and a single quantum well having a preselected thickness between the first barrier region and the second barrier region. The preselected thickness according to embodiments is selected to achieve a predetermined charge density in the quantum well. The predetermined charge density according to embodiments results from a predetermined bias current applied to the semiconductor structure. The predetermined bias current according to embodiments comprises less than about 1 mA.

Abstract: Provided is a light emitting semiconductor structure that operates as a light emitting diode (LED). In embodiments of the invention, the light emitting semiconductor structure includes a first barrier region, a second barrier region, and a single quantum well having a preselected thickness between the first barrier region and the second barrier region. The preselected thickness according to embodiments is selected to achieve a predetermined charge density in the quantum well. The predetermined charge density according to embodiments results from a predetermined bias current applied to the semiconductor structure. The predetermined bias current according to embodiments comprises less than about 1 mA.

Abstract: A method for crystal analysis includes identifying a crystalline region on a device where an electronic channeling pattern is needed to be determined, acquiring a whole image for each of a plurality of different positions for the crystalline region using a scanning electron microscope (SEM) as the crystalline region is moved to different positions. Relevant regions are extracted from the whole images. The images of the relevant regions are stitched together to form a composite map of a full electron channeling pattern representative of the crystalline region wherein the electronic channeling pattern is provided due to an increase in effective angular range between a SEM beam and a surface of the crystal region.

Abstract: A method for crystal analysis includes identifying a crystalline region on a device where an electronic channeling pattern is needed to be determined, acquiring a whole image for each of a plurality of different positions for the crystalline region using a scanning electron microscope (SEM) as the crystalline region is moved to different positions. Relevant regions are extracted from the whole images. The images of the relevant regions are stitched together to form a composite map of a full electron channeling pattern representative of the crystalline region wherein the electronic channeling pattern is provided due to an increase in effective angular range between a SEM beam and a surface of the crystal region.

Abstract: Embodiments are directed to a method of passivating a surface of a high-mobility semiconductor and resulting structures having a reduced interface defect density. A semiconductor layer is formed on a substrate. A surface of the semiconductor layer is contacted with a sulfur source including thiourea at a temperature of up to about 90 degrees Celsius to form a sulfur passivation layer on the surface of the semiconductor layer. A dielectric layer is formed on the sulfur passivation layer and a minimum of interface trap density distribution at an interface between the semiconductor layer and the dielectric layer is less than about 2.0×1011 cm?2 eV?1.

Abstract: Embodiments are directed to a method of passivating a surface of a high-mobility semiconductor and resulting structures having a reduced interface defect density. A semiconductor layer is formed on a substrate. A surface of the semiconductor layer is contacted with a sulfur source including thiourea at a temperature of up to about 90 degrees Celsius to form a sulfur passivation layer on the surface of the semiconductor layer. A dielectric layer is formed on the sulfur passivation layer and a minimum of interface trap density distribution at an interface between the semiconductor layer and the dielectric layer is less than about 2.0×1011 cm?2eV?1.

Abstract: Embodiments are directed to a method of passivating a surface of a high-mobility semiconductor and resulting structures having a reduced interface defect density. A semiconductor layer is formed on a substrate. A surface of the semiconductor layer is contacted with a sulfur source including thiourea at a temperature of up to about 90 degrees Celsius to form a sulfur passivation layer on the surface of the semiconductor layer. A dielectric layer is formed on the sulfur passivation layer and a minimum of interface trap density distribution at an interface between the semiconductor layer and the dielectric layer is less than about 2.0×1011 cm?2 eV?1.

Abstract: An automatic method is provided to align a semiconductor crystalline substrate for electron channeling contrast imaging (ECCI) in regions where an electron channeling pattern cannot be reliably obtained but crystalline defects need to be imaged. The automatic semiconductor crystalline substrate alignment method is more reproducible and faster than the current operator intensive process for ECCI alignment routines. Also, the automatic semiconductor crystalline substrate alignment method increases the throughput of ECCI.

Abstract: An automatic method is provided to align a semiconductor crystalline substrate for electron channeling contrast imaging (ECCI) in regions where an electron channeling pattern cannot be reliably obtained but crystalline defects need to be imaged. The automatic semiconductor crystalline substrate alignment method is more reproducible and faster than the current operator intensive process for ECCI alignment routines. Also, the automatic semiconductor crystalline substrate alignment method increases the throughput of ECCI.

Abstract: Imaging and processing techniques are employed to identify crystalline defects obtained by ECCI from surrounding topography and is combined with defect counting and automatic classification.

Abstract: A multi-beam electron microscope for ECCI is provided. The electron microscope has a platform, on which a crystalline sample is placed. At least a first electron source and a second electron source of the electron microscope are mounted to a housing. The housing is tiltable with respect to a longitudinal direction through a pivot for forming a fulcrum, such that the first electron source and the second electron source are tilted simultaneously and are substantially equally distanced from the platform along a vertical axis when the housing is tilted. The electron microscope also has electron beam focusing assemblies for focusing the electron beams generated by the electron sources onto the crystalline sample to generate backscattered electrons. The electron microscope also has detectors for detecting the backscattered electrons.

Abstract: An electronic item management and archival system for managing and archiving items. Each item includes at least one of image data, audio data, and video data. The system includes a server configured to receive items, archive at least one of the received items to an archive, and retrieve at least one of the archived items from the archive. In some embodiments, the server also includes architecture that supports a pool of threads promoting multiple, independent archive and retrieve operations concurrently.

Abstract: An electronic item management and archival system for managing and archiving items. Each item includes at least one of image data, audio data, and video data. The system includes a server configured to receive items, archive at least one of the received items to an archive, and retrieve at least one of the archived items from the archive. In some embodiments, the server also includes architecture that supports a pool of threads promoting multiple, independent archive and retrieve operations concurrently.

Abstract: An electronic item management and archival system for managing and archiving items. Each item includes at least one of image data, audio data, and video data. The system includes a server configured to receive items, archive at least one of the received items to an archive, and retrieve at least one of the archived items from the archive. In some embodiments, the server also includes architecture that supports a pool of threads promoting multiple, independent archive and retrieve operations concurrently.

Abstract: An electronic item management and archival system for managing and archiving items. Each item includes at least one of image data, audio data, and video data. The system includes a server configured to receive items, archive at least one of the received items to an archive, and retrieve at least one of the archived items from the archive. In some embodiments, the server also includes architecture that supports a pool of threads promoting multiple, independent archive and retrieve operations concurrently.

Abstract: An electronic item management and archival system for managing and archiving items. Each item includes at least one of image data, audio data, and video data. The system includes a server configured to receive items, archive at least one of the received items to an archive, and retrieve at least one of the archived items from the archive. In some embodiments, the server also includes architecture that supports a pool of threads promoting multiple, independent archive and retrieve operations concurrently.