Abstract: Systems and methods for a semiconductor device having a front-end-of-line structure are provided. The semiconductor device may include a dielectric material having a backside formed on a front side of a semiconductor substrate material and a front side, and an interconnect structure extending through the dielectric material. The interconnect structure may be electrically connected to a semiconductor memory array proximate the front side of the dielectric material. The semiconductor device may further have an insulating material encasing at least a portion of the semiconductor memory array and an opening created during back-end-of-line processing through which the active contact surface at the backside of the interconnect structure is exposed for electrical connection.

Abstract: A capacitance sensing device including a semiconductor wafer having a frontside surface and a backside surface, a plurality of capacitance sensing units disposed close to the frontside surface of the semiconductor wafer, a plurality of first electrodes disposed on the backside surface of the semiconductor wafer, each of the plurality of the first electrodes being aligned to corresponding capacitance sensing unit of the plurality of capacitance sensing units, a first plurality of electrical interconnections connecting each of the plurality of capacitance sensing units to a signal processing circuitry, and a second plurality of electrical interconnections connecting each of the plurality of first electrodes to a power source.

Abstract: Some embodiments include an integrated assembly with a semiconductor channel material having a boundary region where a more-heavily-doped region interfaces with a less-heavily-doped region. The more-heavily-doped region and the less-heavily-doped region have the same majority carriers. The integrated assembly includes a gating structure adjacent the semiconductor channel material and having a gating region and an interconnecting region of a common and continuous material. The gating region has a length extending along a segment of the more-heavily-doped region, a segment of the less-heavily-doped region, and the boundary region. The interconnecting region extends laterally outward from the gating region on a side opposite the semiconductor channel region, and is narrower than the length of the gating region. Some embodiments include methods of forming integrated assemblies.

Abstract: Methods, apparatuses, and systems related to a memory device having on its backside one or more integrally-formed structures is described. A memory device may include a backside pad-via structure, a backside redistribution layer structure, or a combination thereof. Such backside structures may include integrally-formed portions that extend in different directions to laterally route electrical signals on the backside.

Abstract: Methods, systems, and devices for die-to-die probe pad connection in a stacked semiconductor device are described. The stacked semiconductor device may include a first probe pad that is on a physically accessible surface of a stack of semiconductor dies. The stacked semiconductor device may include a second probe pad located at a physically inaccessible surface of (e.g., within) the stack of semiconductor dies. And the stacked semiconductor device may include a conductive path that electrically couples the first probe pad with the second probe pad.

Abstract: Methods, systems, and devices for dielectric windows for groups of vias through semiconductor substrates are described. For example, a semiconductor component (e.g., a semiconductor die, a semiconductor wafer) may be formed with one or more dielectric windows through a substrate of the semiconductor component, through which a group of multiple vias may be formed to support signaling with circuitry of the semiconductor component. In some implementations, a set of multiple cavities may be formed through a given dielectric portion and, in each of the multiple cavities, a conductive portion (e.g., one or more conductive materials) may be formed to support multiple electrically isolated contacts. In various examples, such vias may include contacts themselves (e.g., for vias that extend to the surface of the semiconductor component), or may be otherwise coupled with (e.g., contiguous with, electrically coupled with) a contact portion that has a different cross-section than the vias.

Abstract: A method of forming a microelectronic device comprises forming a microelectronic device structure comprising a base structure, a doped semiconductive material overlying the base structure, a stack structure overlying the doped semiconductive material, cell pillar structures vertically extending through the stack structure and the doped semiconductive material and into the base structure, and digit line structures vertically overlying the stack structure. An additional microelectronic device structure comprising control logic devices is formed. The microelectronic device structure is attached to the additional microelectronic device structure to form a microelectronic device structure assembly. The base structure and portions of the cell pillar structures vertically extending into the base structure are removed to expose the doped semiconductive material. The doped semiconductive material is then patterned to form at least one source structure over the stack structure and coupled to the cell pillar structures.

Abstract: Systems and methods for a semiconductor device having a front-end-of-line interconnect structure are provided. The semiconductor device may include a dielectric material having a backside formed on a front side of a semiconductor or silicon substrate material and a front side, and a conducting material on the front side of the dielectric material. The conducting material may have a line portion and an interconnect structure electrically coupled to the line portion and separated from the front side of the substrate material by the dielectric material. The interconnect structure has a backside defining a contact surface. The semiconductor device may further include a semiconductor die proximate the front side of the dielectric material, an insulating material encasing at least a portion of the semiconductor die, and an opening through which the active contact surface at the backside of the interconnect structure is exposed for electrical connection.

Abstract: A semiconductor device assembly is disclosed. The semiconductor device assembly includes a semiconductor substrate on which a plurality of semiconductor dies are implemented. The semiconductor substrate includes a scribe area between the plurality of semiconductor dies. A layer of passivation material is disposed at a first side of the semiconductor substrate such that the layer of passivation material has one or more recessed portions at the scribe area.

Abstract: Methods, systems, and devices for memory with parallel main and test interfaces are described. A memory die may be configured with parallel interfaces that may individually (e.g., separately) support evaluation operations (e.g., before or as part of assembly in a multiple-die stack) or access operations (e.g., after assembly in a multiple die stack). For example, a memory die may include a first set of one or more contacts that support communicating signaling with or via another memory die in a multiple-die stack. The memory die may also include a second set of one or more contacts that support probing for pre-assembly evaluations, which may be electrically isolated from the first set of contacts. By implementing such parallel interfaces, evaluation operations may be performed using the second set of contacts without damaging the first set of contacts, which may improve capabilities for supporting a multiple-die stack in a memory device.

Abstract: A semiconductor device assembly is provided. The assembly includes a first semiconductor device including a plurality of electrical contacts on an upper surface thereof; a monolithic silicon structure having a lower surface in contact with the upper surface of the first semiconductor device, the monolithic silicon structure including a cavity extending from the lower surface completely through a body of the monolithic silicon structure to a top surface of the monolithic silicon structure; and a second semiconductor device disposed in the cavity, the second semiconductor device including a plurality of interconnects, each operatively coupled to a corresponding one of the plurality of electrical contacts.

Abstract: A method used in forming a vertical string of memory cells and a conductive via comprises forming a first lower opening and a second lower opening into a lower material. A first material is formed within the first and second lower openings. An upper material is formed above the lower material and above the first material in the first and second lower openings. A first upper opening is formed through the upper material to the first material in the first lower opening. At least a majority of the first material is removed from the first lower opening through the first upper opening and channel material is formed within the first lower and first upper openings for the vertical string of memory cells being formed. After forming the channel material, a second upper opening is formed through the upper material to the first material in the second lower opening. Conductive material of the conductive via is formed within the second upper opening. Structure embodiments independent of method of formation are disclosed.

Abstract: A microelectronic device comprises a memory array region, a control logic region, and an additional control logic region. The memory array region comprises a stack structure comprising vertically alternating conductive structures and insulating structures, and vertically extending strings of memory cells within the stack structure. The control logic region underlies the stack structure and comprises control logic devices configured to effectuate a portion of control operations for the vertically extending strings of memory cells. The additional control logic region overlies the stack structure and comprises additional control logic devices configured to effectuate an additional portion of the control operations for the vertically extending strings of memory cells. Methods of forming a microelectronic device, and additional microelectronic devices and electronic systems are also described.

Abstract: A method of forming a microelectronic device comprises forming line structures comprising conductive material and insulative material overlying the conductive material, the line structures separated from one another by trenches. An isolation material is formed on surfaces of the line structures inside and outside of the trenches, the isolation material only partially filling the trenches to form air gaps interposed between the line structures. Openings are formed to extend through the isolation material and expose portions of the insulative material of the line structures. The exposed portions of the insulative material of the line structures are removed to form extended openings extending to the conductive material of the line structures. Conductive contact structures are formed within the extended openings. Conductive pad structures are formed on the conductive contact structures. Additional methods, microelectronic devices, memory devices, and electronic systems are also described.

Abstract: A semiconductor device assembly is disclosed. The semiconductor device assembly includes a first semiconductor die and second semiconductor dies and an additional semiconductor component coupled with the logic die. Dielectric peripheral material is disposed along sidewalls of the first die and extends beyond a first footprint of the first die. A gap fill material is disposed at the first die and at the dielectric peripheral material beyond a second footprint of the second semiconductor dies and a third footprint of the additional semiconductor component such that the gap fill material at least partially surrounds the second semiconductor dies and the additional semiconductor component.

Abstract: Some embodiments include an integrated assembly with a semiconductor channel material having a boundary region where a more-heavily-doped region interfaces with a less-heavily-doped region. The more-heavily-doped region and the less-heavily-doped region have the same majority carriers. The integrated assembly includes a gating structure adjacent the semiconductor channel material and having a gating region and an interconnecting region of a common and continuous material. The gating region has a length extending along a segment of the more-heavily-doped region, a segment of the less-heavily-doped region, and the boundary region. The interconnecting region extends laterally outward from the gating region on a side opposite the semiconductor channel region, and is narrower than the length of the gating region. Some embodiments include methods of forming integrated assemblies.

Abstract: A semiconductor device having monolithic conductive columns, and associated systems and methods, are disclosed herein. The semiconductor device can include a semiconductor die and a molding material. The semiconductor die may have a semiconductor substrate, a conductive pad, an opening, a non-conductive liner, and a plug of non-conductive material. The conductive pad may be at a surface of the semiconductor substrate. The opening may extend through the semiconductor substrate from the conductive pad to a second surface and define a side wall. The liner may coat the side wall and the plug may fill the opening. A second opening may be formed through the semiconductor device and the opening and a conductive material plated therein. The molding material may be laterally adjacent to the semiconductor die.

Abstract: Some embodiments include an integrated structure having a conductive material, a select device gate material over the conductive material, and vertically-stacked conductive levels over the select device gate material. Vertically-extending monolithic channel material is adjacent the select device gate material and the conductive levels. The monolithic channel material contains a lower segment adjacent the select device gate material and an upper segment adjacent the conductive levels. A first vertically-extending region is between the lower segment of the monolithic channel material and the select device gate material. The first vertically-extending region contains a first material. A second vertically-extending region is between the upper segment of the monolithic channel material and the conductive levels. The second vertically-extending region contains a material which is different in composition from the first material.

Abstract: A method for forming a semiconductor device assembly is described. The method comprises vertically stacking at least one semiconductor device over a substrate; and ink-jet printing, after vertically stacking the at least one semiconductor device, a conductive pad on an exposed conductor of the at least one semiconductor device or of the substrate. The method can further include testing an electrical circuit of the semiconductor device assembly by electrically probing the electrical circuit through the conductive pad.

Abstract: A method for modifying a geometry of a wafer comprises measuring a local geometry for each of a plurality edge locations of the wafer, determining, based on the measured local geometry, an amount of additional material for each of the plurality of locations of the wafer calculated to provide a desired wafer-level geometry for the wafer, and dispensing, from a printing nozzle, the determined amount of additional material at each of the plurality of locations of the wafer to provide the wafer with the desired wafer-level geometry.