Abstract: The invention includes a number of methods and structures pertaining to semiconductor circuit technology, including: methods of forming DRAM memory cell constructions; methods of forming capacitor constructions; DRAM memory cell constructions; capacitor constructions; and monolithic integrated circuitry. The invention includes a method of forming a capacitor comprising the following steps: a) forming a mass of silicon material over a node location, the mass comprising exposed doped silicon and exposed undoped silicon; b) substantially selectively forming rugged polysilicon from the exposed undoped silicon and not from the exposed doped silicon; and c) forming a capacitor dielectric layer and a complementary capacitor plate proximate the rugged polysilicon and doped silicon.

Abstract: Methods are disclosed for forming shaped structures of silicon-containing material with ion implantation and an etching process which is selective to silicon-containing material implanted to a certain concentration of ions or with an etching process which is selective to relatively unimplanted silicon-containing material. In general, the methods initially involve providing a layer of silicon-containing material such as polysilicon or epitaxial silicon on a semiconductor substrate. The layer of silicon-containing material is then masked, and ions are implanted into exposed portions of the layer of silicon-containing material. The mask is removed, and the aforementioned selective etching process is conducted to result in one of an implanted and a relatively unimplanted portion of the layer of silicon-containing material being etched away and the other left standing to form a shaped structure of silicon-containing material.

Abstract: The invention includes a number of methods and structures pertaining to semiconductor circuit technology, including: methods of forming DRAM memory cell constructions; methods of forming capacitor constructions; DRAM memory cell constructions; capacitor constructions; and monolithic integrated circuitry. The invention includes a method of forming a capacitor comprising the following steps: a) forming a mass of silicon material over a node location, the mass comprising exposed doped silicon and exposed undoped silicon; b) substantially selectively forming rugged polysilicon from the exposed undoped silicon and not from the exposed doped silicon; and c) forming a capacitor dielectric layer and a complementary capacitor plate proximate the rugged polysilicon and doped silicon.

Abstract: The invention includes a number of methods and structures pertaining to semiconductor circuit technology, including: methods of forming DRAM memory cell constructions; methods of forming capacitor constructions; DRAM memory cell constructions; capacitor constructions; and monolithic integrated circuitry. The invention includes a method of forming a capacitor comprising the following steps: a) forming a mass of silicon material over a node location, the mass comprising exposed doped silicon and exposed undoped silicon; b) substantially selectively forming rugged polysilicon from the exposed undoped silicon and not from the exposed doped silicon; and c) forming a capacitor dielectric layer and a complementary capacitor plate proximate the rugged polysilicon and doped silicon.

Abstract: A method of making a capacitor comprising providing a space extending between a pair of gate stacks on a semiconductor substrate, the space exposing a charge conducting region on the semiconductor substrate. A BPSG layer is formed over the pair of gate stacks. A hard mask layer comprising alternating layers of doped polysilicon and undoped polysilicon is formed over the BPSG layer during a single deposition cycle of depositing polysilicon. Portions of the hard mask layer and the BPSG layer are selectively removed to form topographical structures extending above the gate stacks and having a trench therebetween. A spacer etch and a contact etch are performed to expose the charge conducting region. A doped polysilicon spacer is formed on the lateral side of each topographical structure. A second group of alternating layers of doped polysilicon and undoped polysilicon is formed over the topographical structures and within the trench.

Abstract: The invention encompasses DRAM constructions, capacitor constructions, integrated circuitry, and methods of forming DRAM constructions, integrated circuitry and capacitor constructions. The invention encompasses a method of forming a capacitor wherein: a) a first layer is formed; b) a semiconductive material masking layer is formed over the first layer; c) an opening is etched through the masking layer and first layer to a node; d) a storage node layer is formed within the opening and in electrical connection with the masking layer; e) a capacitor storage node is formed from the masking layer and the storage node layer; and f) a capacitor dielectric layer and outer capacitor plate are formed operatively proximate the capacitor storage node.

Abstract: A double blanket ion implant method for forming diffusion regions in memory array devices, such as a MOSFET access device is disclosed. The method provides a semiconductor substrate with a gate structure formed on its surface Next, a first pair of diffusion regions are formed in a region adjacent to the channel region by a first blanket ion implantation process. The first blanket ion implantation process has a first energy level and dose. The device is subjected to oxidizing conditions, which form oxidized sidewalls on the gate structure. A second blanket ion implantation process is conducted at the same location as the first ion implantation process adding additional dopant to the diffusion regions. The second blanket ion implantation process has a second energy level and dose. The resultant diffusion regions provide the device with improved static refresh performance over prior art devices.

Abstract: The invention encompasses DRAM constructions, capacitor constructions, integrated circuitry, and methods of forming DRAM constructions, integrated circuitry and capacitor constructions. The invention encompasses a method of forming a capacitor wherein: a) a first layer is formed; b) a semiconductive material masking layer is formed over the first layer; c) an opening is etched through the masking layer and first layer to a node; d) a storage node layer is formed within the opening and in electrical connection with the masking layer; e) a capacitor storage node is formed from the masking layer and the storage node layer; and f) a capacitor dielectric layer and outer capacitor plate are formed operatively proximate the capacitor storage node.

Abstract: Disclosed is a method of forming a self-aligned contact to a semiconductor substrate by use of a sacrificial spacer. The sacrificial spacer has the advantage of self aligning metallization to the semiconductive substrate or to a polysilicon plug material without extra photolithography steps as are required in the prior art.

Abstract: The invention includes a number of methods and structures pertaining to semiconductor circuit technology, including: methods of forming DRAM memory cell constructions; methods of forming capacitor constructions; DRAM memory cell constructions; capacitor constructions; and monolithic integrated circuitry. The invention includes a method of forming a capacitor comprising the following steps: a) forming a mass of silicon material over a node location, the mass comprising exposed doped silicon and exposed undoped silicon; b) substantially selectively forming rugged polysilicon from the exposed undoped silicon and not from the exposed doped silicon; and c) forming a capacitor dielectric layer and a complementary capacitor plate proximate the rugged polysilicon and doped silicon.

Abstract: In one aspect, the invention includes an isolation region forming method comprising: a) forming an oxide layer over a substrate; b) forming a nitride layer over the oxide layer, the nitride layer and oxide layer having a pattern of openings extending therethrough to expose portions of the underlying substrate; c) etching the exposed portions of the underlying substrate to form openings extending into the substrate; d) after etching the exposed portions of the underlying substrate, removing portions of the nitride layer while leaving some of the nitride layer remaining over the substrate; and e) after removing portions of the nitride layer, forming oxide within the openings in the substrate, the oxide within the openings forming at least portions of isolation regions.

Abstract: The invention encompasses methods of forming DRAM constructions, methods of forming capacitor constructions, DRAM constructions, and capacitor constructions. The invention includes a method in which a) a first layer is formed over a node location; b) a semiconductive material masking layer is formed over the first layer; c) an opening is formed through the semiconductive material masking layer and the first layer to the node location; d) an upwardly open capacitor storage node layer is formed within the opening; e) a storage node is formed from the masking layer and the storage node layer; and f) a capacitor dielectric layer and a capacitor plate are formed over the storage node.

Abstract: Methods of electrically contacting to conductive plugs, methods of forming contact openings, and methods of forming dynamic random access memory circuitry are described. In one embodiment, a pair of conductive contact plugs are formed to project outwardly relative to a semiconductor wafer. The plugs have respective tops, one of which being covered with different first and second insulating materials. An opening is etched through one of the first and second insulating materials to expose only one of the tops of the pair of plugs. Electrically conductive material is formed within the opening and in electrical connection with the one plug. In a preferred embodiment, two-spaced apart conductive lines are formed over a substrate and conductive plugs are formed between, and on each side of the conductive lines. The conductive plug formed between the conductive lines provides a bit line contact plug having an at least partially exposed top portion.

Abstract: The present invention is directed toward building a microelectronic device in which a semiconductor substrate has thereon an etch buffer layer used in a processing method in which the buffer layer will act as an etch uniformity aid. In a method of making the microelectronic device, a semiconductor substrate is covered with an etch buffer layer and with an insulative layer. A first etch is performed by patterning and etching through a mask. The first etch penetrates the insulative layer, forms a cavity therein, and is selective to the buffer layer so as to expose the buffer layer. A second etch is performed that is selective to the insulative layer and the semiconductor substrate, and is not selective to the buffer layer. The buffer layer can be an insulative material of a type other than the material of the insulative layer or the buffer layer can also be of a conductive material.

Abstract: In one aspect, the invention includes an isolation region forming method comprising: a) forming an oxide layer over a substrate; b) forming a nitride layer over the oxide layer, the nitride layer and oxide layer having a pattern of openings extending therethrough to expose portions of the underlying substrate; c) etching the exposed portions of the underlying substrate to form openings extending into the substrate; d) after etching the exposed portions of the underlying substrate, removing portions of the nitride layer while leaving some of the nitride layer remaining over the substrate; and e) after removing portions of the nitride layer, forming oxide within the openings in the substrate, the oxide within the openings forming at least portions of isolation regions.

Abstract: Methods are disclosed for forming shaped structures from silicon and/or germanium containing material with a material removal process that is selective to low stress portions of the material. In general, the method initially provides a layer of the material on a semiconductor substrate. The material, which has uniform stress therein, is then masked, and the stress in a portion of the material is reduced, such as by implanting ions into an unmasked portion. The mask is removed, and the high stress masked portion of the material is selectively removed, preferably by an etching process. The low stress portion of the material remains and forms a shaped structure. One preferred selective etching process uses a basic etchant. The various methods are used to form raised shaped structures, shaped openings, polysilicon plugs, capacitor storage nodes, surround-gate transistors, free-standing walls, interconnect lines, trench capacitors, and trench isolation regions.

Abstract: A method and resulting structure for reducing refraction and reflection occurring at the interface between adjacent layers of different materials in a semiconductor device, assembly or laminate during an alignment step in a semiconductor device fabrication process. The method comprises forming a planar-surfaced layer of material, having a first index of refraction, over a substrate of the semiconductor device, assembly or laminate. A corrective layer is formed over the planar-surfaced layer and a second layer, having a second index of refraction, is then formed over the corrective layer. The corrective layer is composed of a material having an intermediate index of refraction between the first index of refraction and the second index of refraction. The method can also be modified to include one or more layers of materials and/or intermediate refraction layers interposed between or above any of the aforementioned adjacent layers.

Abstract: In one aspect, the invention includes an isolation region forming method comprising: a) forming an oxide layer over a substrate; b) forming a nitride layer over the oxide layer, the nitride layer and oxide layer having a pattern of openings extending therethrough to expose portions of the underlying substrate; c) etching the exposed portions of the underlying substrate to form openings extending into the substrate; d) after etching the exposed portions of the underlying substrate, removing portions of the nitride layer while leaving some of the nitride layer remaining over the substrate; and e) after removing portions of the nitride layer, forming oxide within the openings in the substrate, the oxide within the openings forming at least portions of isolation regions.

Abstract: The invention encompasses DRAM constructions, capacitor constructions, integrated circuitry, and methods of forming DRAM constructions, integrated circuitry and capacitor constructions. The invention encompasses a method of forming a capacitor wherein: a) a first layer is formed; b) a semiconductive material masking layer is formed over the first layer; c) an opening is etched through the masking layer and first layer to a node; d) a storage node layer is formed within the opening and in electrical connection with the masking layer; e) a capacitor storage node is formed from the masking layer and the storage node layer; and f) a capacitor dielectric layer and outer capacitor plate are formed operatively proximate the capacitor storage node.

Abstract: An etch of a fuse opening in overlying layers above a laser-blowable semiconductor fuse having a silicon nitride cap and silicon nitride spacers begins with a silicon nitride that is enclosed in a polysilicon conductive layer on a semiconductor wafer. The etch is performed by etching first with an etch process that etches silicon nitride and later with an etch process that is selective to silicon nitride. The later etch process etches the silicon nitride of the cap and spacers little or not at all, allowing a wider variation in etch depths without destroying the fuse. Also, a patch may be provided in the overlying layers above the fuse, and an etch process employed at the level of the patch that is selective to a material of the patch, resulting in an etch stop effect at that level. The etch process is then changed to an etch process that is not selective to a material of the patch, resulting in decreased variation in etch depth over the surface of the wafer.