Patents by Inventor KUNFENG ZHU

KUNFENG ZHU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor cell structure and power semiconductor device
    Patent number: 10483358
    Abstract: A semiconductor cell structure and power semiconductor device, wherein, the semiconductor cell structure includes: a highly-doped semiconductor material region, an epitaxial layer, a dielectric insulating layer, a semi-insulating material, and an active device region, a deep groove is further etched on the epitaxial layer, the deep groove vertically extends into the highly-doped semiconductor material region, the dielectric insulating layer is formed on a side wall inside the deep groove, and the deep groove is filled with the semi-insulating material. The cell structure can be applied to the power semiconductor device during actual application, the present invention dramatically reduces the difficulty of the process implementation, relaxes the harsh requirements on charge balance, broadens the tolerant charge mismatch percentage by approximately ten times, and also improves the long-term reliability of normal operation of the device cell at the same time.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: November 19, 2019
    Assignee: NO. 24 RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATION
    Inventors: Kaizhou Tan, Gangyi Hu, Zhaohuan Tang, Jianan Wang, Yonghui Yang, Yi Zhong, Yang Cao, Yong Liu, Kunfeng Zhu
  • SEMICONDUCTOR CELL STRUCTURE AND POWER SEMICONDUCTOR DEVICE
    Publication number: 20190027563
    Abstract: A semiconductor cell structure and power semiconductor device, wherein, the semiconductor cell structure includes: a highly-doped semiconductor material region, an epitaxial layer, a dielectric insulating layer, a semi-insulating material, and an active device region, a deep groove is further etched on the epitaxial layer, the deep groove vertically extends into the highly-doped semiconductor material region, the dielectric insulating layer is formed on a side wall inside the deep groove, and the deep groove is filled with the semi-insulating material. The cell structure can be applied to the power semiconductor device during actual application, the present invention dramatically reduces the difficulty of the process implementation, relaxes the harsh requirements on charge balance, broadens the tolerant charge mismatch percentage by approximately ten times, and also improves the long-term reliability of normal operation of the device cell at the same time.
    Type: Application
    Filed: April 1, 2016
    Publication date: January 24, 2019
    Applicant: No. 24 Research Institute of China Electronics Technology Group Corporation
    Inventors: KAIZHOU TAN, GANGYI HU, ZHAOHUAN TANG, JIANAN WANG, YONGHUI YANG, YI ZHONG, YANG CAO, YONG LIU, KUNFENG ZHU