Patents by Inventor Kung-Chen Yeh
Kung-Chen Yeh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10269731Abstract: Apparatus for performing dicing of die on wafer interposers. Apparatuses are disclosed for use with the methods of dicing an interposer having integrated circuit dies mounted thereon. An apparatus includes a wafer carrier mounted in a frame and having a size corresponding to a silicon interposer, a fixture mounted to the wafer carrier and comprising a layer of material to provide mechanical support to the die side of the silicon interposer, the fixture being patterned to fill spaces between integrated circuit dies mounted on an interposer; and an adhesive tape disposed on a surface of the fixture for adhering to the surface of a silicon interposer. Additional alternative apparatuses are disclosed.Type: GrantFiled: February 2, 2015Date of Patent: April 23, 2019Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung Yu Wang, Kung-Chen Yeh, Chih-Wei Wu, Szu-Wei Lu, Jing-Cheng Lin
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Patent number: 9793187Abstract: Embodiments of the present disclosure include a semiconductor device and methods of forming a semiconductor device. An embodiment is a method of forming a semiconductor device, the method including bonding a die to a top surface of a first substrate, the die being electrically coupled to the first substrate, and forming a support structure on the top surface of the first substrate, the support structure being physically separated from the die with a top surface of the support structure being coplanar with a top surface of the die. The method further includes performing a sawing process on the first substrate, the sawing process sawing through the support structure.Type: GrantFiled: August 17, 2015Date of Patent: October 17, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shih Ting Lin, Kung-Chen Yeh, Szu-Wei Lu, Jing-Cheng Lin
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Patent number: 9337063Abstract: A wafer level package includes a semiconductor die bonded on a supporting wafer. The semiconductor die has at least a step recess at its substrate. An underfill layer is formed between the semiconductor die and the supporting wafer. Moreover, the height of the underfill layer is limited by the step recess. During a fabrication process of the wafer level package, the step recess helps to reduce the stress on the wafer level package.Type: GrantFiled: July 3, 2014Date of Patent: May 10, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Hao Chen, Long Hua Lee, Chun-Hsing Su, Yi-Lin Tsai, Kung-Chen Yeh, Chung Yu Wang, Jui-Pin Hung, Jing-Cheng Lin
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Publication number: 20150357255Abstract: Embodiments of the present disclosure include a semiconductor device and methods of forming a semiconductor device. An embodiment is a method of forming a semiconductor device, the method including bonding a die to a top surface of a first substrate, the die being electrically coupled to the first substrate, and forming a support structure on the top surface of the first substrate, the support structure being physically separated from the die with a top surface of the support structure being coplanar with a top surface of the die. The method further includes performing a sawing process on the first substrate, the sawing process sawing through the support structure.Type: ApplicationFiled: August 17, 2015Publication date: December 10, 2015Inventors: Shih Ting Lin, Kung-Chen Yeh, Szu-Wei Lu, Jing-Cheng Lin
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Patent number: 9111912Abstract: Embodiments of the present disclosure include a semiconductor device and methods of forming a semiconductor device. An embodiment is a method of forming a semiconductor device, the method including bonding a die to a top surface of a first substrate, the die being electrically coupled to the first substrate, and forming a support structure on the top surface of the first substrate, the support structure being physically separated from the die with a top surface of the support structure being coplanar with a top surface of the die. The method further includes performing a sawing process on the first substrate, the sawing process sawing through the support structure.Type: GrantFiled: August 30, 2013Date of Patent: August 18, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shih Ting Lin, Kung-Chen Yeh, Szu Wei Lu, Jing-Cheng Lin
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Publication number: 20150145133Abstract: Apparatus for performing dicing of die on wafer interposers. Apparatuses are disclosed for use with the methods of dicing an interposer having integrated circuit dies mounted thereon. An apparatus includes a wafer carrier mounted in a frame and having a size corresponding to a silicon interposer, a fixture mounted to the wafer carrier and comprising a layer of material to provide mechanical support to the die side of the silicon interposer, the fixture being patterned to fill spaces between integrated circuit dies mounted on an interposer; and an adhesive tape disposed on a surface of the fixture for adhering to the surface of a silicon interposer. Additional alternative apparatuses are disclosed.Type: ApplicationFiled: February 2, 2015Publication date: May 28, 2015Inventors: Chung Yu Wang, Kung-Chen Yeh, Chih-Wei Wu, Szu-Wei Lu, Jing-Cheng Lin
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Patent number: 8946893Abstract: Apparatus for performing dicing of die on wafer interposers. Apparatuses are disclosed for use with the methods of dicing an interposer having integrated circuit dies mounted thereon. An apparatus includes a wafer carrier mounted in a frame and having a size corresponding to a silicon interposer, a fixture mounted to the wafer carrier and comprising a layer of material to provide mechanical support to the die side of the silicon interposer, the fixture being patterned to fill spaces between integrated circuit dies mounted on an interposer; and an adhesive tape disposed on a surface of the fixture for adhering to the surface of a silicon interposer. Additional alternative apparatuses are disclosed.Type: GrantFiled: June 25, 2013Date of Patent: February 3, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung Yu Wang, Kung-Chen Yeh, Chih-Wei Wu, Szu Wei Lu, Jing-Cheng Lin
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Publication number: 20140353838Abstract: Embodiments of the present disclosure include a semiconductor device and methods of forming a semiconductor device. An embodiment is a method of forming a semiconductor device, the method including bonding a die to a top surface of a first substrate, the die being electrically coupled to the first substrate, and forming a support structure on the top surface of the first substrate, the support structure being physically separated from the die with a top surface of the support structure being coplanar with a top surface of the die. The method further includes performing a sawing process on the first substrate, the sawing process sawing through the support structure.Type: ApplicationFiled: August 30, 2013Publication date: December 4, 2014Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shih Ting Lin, Kung-Chen Yeh, Szu Wei Lu, Jing-Cheng Lin
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Publication number: 20140322866Abstract: A wafer level package includes a semiconductor die bonded on a supporting wafer. The semiconductor die has at least a step recess at its substrate. An underfill layer is formed between the semiconductor die and the supporting wafer. Moreover, the height of the underfill layer is limited by the step recess. During a fabrication process of the wafer level package, the step recess helps to reduce the stress on the wafer level package.Type: ApplicationFiled: July 3, 2014Publication date: October 30, 2014Inventors: Chih-Hao Chen, Long Hua Lee, Chun-Hsing Su, Yi-Lin Tsai, Kung-Chen Yeh, Chung Yu Wang, Jui-Pin Hung, Jing-Cheng Lin
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Patent number: 8772929Abstract: A wafer level package includes a semiconductor die bonded on a supporting wafer. The semiconductor die has at least a step recess at its substrate. An underfill layer is formed between the semiconductor die and the supporting wafer. Moreover, the height of the underfill layer is limited by the step recess. During a fabrication process of the wafer level package, the step recess helps to reduce the stress on the wafer level package.Type: GrantFiled: November 16, 2011Date of Patent: July 8, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Hao Chen, Long Hua Lee, Chun-Hsing Su, Yi-Lin Tsai, Kung-Chen Yeh, Chung Yu Wang, Jui-Pin Hung, Jing-Cheng Lin
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Patent number: 8629043Abstract: A method includes performing a dicing on a composite wafer including a plurality of dies, wherein the composite wafer is bonded on a carrier when the step of dicing is performed. After the step of dicing, the composite wafer is mounted onto a tape. The carrier is then de-bonded from the composite wafer and the first tape.Type: GrantFiled: November 16, 2011Date of Patent: January 14, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung Yu Wang, Jui-Pin Hung, Chih-Hao Chen, Chun-Hsing Su, Yi-Chao Mao, Kung-Chen Yeh, Yi-Lin Tsai, Ying-Tz Hung, Chin-Fu Kao, Shih-Yi Syu, Chin-Chuan Chang, Hsien-Wen Liu, Long Hua Lee
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Publication number: 20130285241Abstract: Apparatus for performing dicing of die on wafer interposers. Apparatuses are disclosed for use with the methods of dicing an interposer having integrated circuit dies mounted thereon. An apparatus includes a wafer carrier mounted in a frame and having a size corresponding to a silicon interposer, a fixture mounted to the wafer carrier and comprising a layer of material to provide mechanical support to the die side of the silicon interposer, the fixture being patterned to fill spaces between integrated circuit dies mounted on an interposer; and an adhesive tape disposed on a surface of the fixture for adhering to the surface of a silicon interposer. Additional alternative apparatuses are disclosed.Type: ApplicationFiled: June 25, 2013Publication date: October 31, 2013Inventors: Chung Yu Wang, Kung-Chen Yeh, Chih-Wei Wu, Szu Wei Lu, Jing-Cheng Lin
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Patent number: 8501590Abstract: Methods and apparatus for performing dicing of die on wafer interposers. Methods are disclosed that include receiving an interposer assembly including one or more integrated circuit dies mounted on a die side of an interposer substrate and having scribe areas defined in spaces between the integrated circuit dies, the interposer having an opposite side for receiving external connectors; mounting the die side of the interposer assembly to a tape assembly, the tape assembly comprising an adhesive tape and preformed spacers disposed between and filling gaps between the integrated circuit dies; and sawing the interposer assembly by cutting the opposite side of the interposer in the scribe areas to make cuts through the interposer, the cuts separating the interposer into one or more die on wafer assemblies. Apparatuses are disclosed for use with the methods.Type: GrantFiled: July 5, 2011Date of Patent: August 6, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung Yu Wang, Kung-Chen Yeh, Chih-Wei Wu, Szu Wei Lu, Jing-Cheng Lin
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Publication number: 20130122689Abstract: A method includes performing a dicing on a composite wafer including a plurality of dies, wherein the composite wafer is bonded on a carrier when the step of dicing is performed. After the step of dicing, the composite wafer is mounted onto a tape. The carrier is then de-bonded from the composite wafer and the first tape.Type: ApplicationFiled: November 16, 2011Publication date: May 16, 2013Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung Yu Wang, Jui-Pin Hung, Chih-Hao Chen, Chun-Hsing Su, Yi-Chao Mao, Kung-Chen Yeh, Yi-Lin Tsai, Ying-Tz Hung, Chin-Fu Kao, Shih-Yi Syu, Chin-Chuan Chang, Hsien-Wen Liu, Long Hua Lee
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Publication number: 20130119533Abstract: A wafer level package includes a semiconductor die bonded on a supporting wafer. The semiconductor die has at least a step recess at its substrate. An underfill layer is formed between the semiconductor die and the supporting wafer. Moreover, the height of the underfill layer is limited by the step recess. During a fabrication process of the wafer level package, the step recess helps to reduce the stress on the wafer level package.Type: ApplicationFiled: November 16, 2011Publication date: May 16, 2013Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Hao Chen, Long Hua Lee, Chun-Hsing Su, Yi-Lin Tsai, Kung-Chen Yeh, Chung Yu Wang, Jui-Pin Hung, Jing-Cheng Lin
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Publication number: 20130009316Abstract: Methods and apparatus for performing dicing of die on wafer interposers. Methods are disclosed that include receiving an interposer assembly including one or more integrated circuit dies mounted on a die side of an interposer substrate and having scribe areas defined in spaces between the integrated circuit dies, the interposer having an opposite side for receiving external connectors; mounting the die side of the interposer assembly to a tape assembly, the tape assembly comprising an adhesive tape and preformed spacers disposed between and filling gaps between the integrated circuit dies; and sawing the interposer assembly by cutting the opposite side of the interposer in the scribe areas to make cuts through the interposer, the cuts separating the interposer into one or more die on wafer assemblies. Apparatuses are disclosed for use with the methods.Type: ApplicationFiled: July 5, 2011Publication date: January 10, 2013Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung Yu Wang, Kung-Chen Yeh, Chih-Wei Wu, Szu Wei Lu, Jing-Cheng Lin