Patents by Inventor Kung-Hong Lee

Kung-Hong Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10475738
    Abstract: A semiconductor device preferably includes: a first metal-oxide semiconductor (MOS) transistor on a substrate; a first ferroelectric (FE) layer connected to the first MOS transistor; a second MOS transistor on the substrate; and a second FE layer connected to the second MOS transistor. Preferably, the first FE layer and the second FE layer include different capacitance.
    Type: Grant
    Filed: December 27, 2016
    Date of Patent: November 12, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Kung-Hong Lee, Mu-Kai Tsai, Chung-Hsing Lin
  • Publication number: 20180182860
    Abstract: A semiconductor device preferably includes: a first metal-oxide semiconductor (MOS) transistor on a substrate; a first ferroelectric (FE) layer connected to the first MOS transistor; a second MOS transistor on the substrate; and a second FE layer connected to the second MOS transistor. Preferably, the first FE layer and the second FE layer include different capacitance.
    Type: Application
    Filed: December 27, 2016
    Publication date: June 28, 2018
    Inventors: Kung-Hong Lee, Mu-Kai Tsai, Chung-Hsing Lin
  • Patent number: 9741830
    Abstract: The present invention provides a method of forming a metal oxide semiconductor (MOS) device comprising a gate structure and an epitaxial structure. The gate structure is disposed on a substrate. The epitaxial structure is disposed in the substrate at two sides of the gate structure and a part thereof serves a source/drain of the MOS, wherein the epitaxial structure comprises: a first buffer layer with a second conductive type, a second buffer layer, and an epitaxial layer with a first conductive type complementary to the second conductive type. The present invention further provides a method of forming the same.
    Type: Grant
    Filed: April 7, 2016
    Date of Patent: August 22, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Kung-Hong Lee, Chun-Jung Tang, Te-Chih Chen, Tai-Ju Chen
  • Publication number: 20160225880
    Abstract: The present invention provides a method of forming a metal oxide semiconductor (MOS) device comprising a gate structure and an epitaxial structure. The gate structure is disposed on a substrate. The epitaxial structure is disposed in the substrate at two sides of the gate structure and a part thereof serves a source/drain of the MOS, wherein the epitaxial structure comprises: a first buffer layer with a second conductive type, a second buffer layer, and an epitaxial layer with a first conductive type complementary to the second conductive type. The present invention further provides a method of forming the same.
    Type: Application
    Filed: April 7, 2016
    Publication date: August 4, 2016
    Inventors: Kung-Hong Lee, Chun-Jung Tang, Te-Chih Chen, Tai-Ju Chen
  • Publication number: 20160155837
    Abstract: The present invention provides a metal oxide semiconductor (MOS) device, comprising a gate structure and an epitaxial structure. The gate structure is disposed on a substrate. The epitaxial structure is disposed in the substrate at two sides of the gate structure and apart thereof serves a source/drain of the MOS, wherein the epitaxial structure comprises: a first buffer layer with a second conductive type, a second buffer layer, and an epitaxial layer with a first conductive type complementary to the second conductive type. The present invention further provides a method of forming the same.
    Type: Application
    Filed: December 27, 2014
    Publication date: June 2, 2016
    Inventors: Kung-Hong Lee, Chun-Jung Tang, Te-Chih Chen, Tai-Ju Chen
  • Patent number: 9337339
    Abstract: The present invention provides a metal oxide semiconductor (MOS) device, comprising a gate structure and an epitaxial structure. The gate structure is disposed on a substrate. The epitaxial structure is disposed in the substrate at two sides of the gate structure and apart thereof serves a source/drain of the MOS, wherein the epitaxial structure comprises: a first buffer layer with a second conductive type, a second buffer layer, and an epitaxial layer with a first conductive type complementary to the second conductive type. The present invention further provides a method of forming the same.
    Type: Grant
    Filed: December 27, 2014
    Date of Patent: May 10, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Kung-Hong Lee, Chun-Jung Tang, Te-Chih Chen, Tai-Ju Chen
  • Patent number: 7598795
    Abstract: A negative voltage converter includes six transistors. A first end and a control end of a first transistor are coupled to a signal input. A first end of a second transistor is coupled to the signal input, and a control end of which is coupled to a first clock and the first transistor. A first end of a third transistor is coupled to the signal input, a control end of the third transistor is coupled with a second clock and the second transistor. A first end of a fourth transistor is coupled to the second end of the third transistor, a control end of which is coupled with the first clock and the third transistor. A first end of a fifth transistor is coupled to the second end of the third transistor, and a control end of which is coupled with the second clock and the fourth transistor A first end of a sixth transistor is coupled to the second end of the third transistor, and a control end of which is coupled with the first clock and the fifth transistor.
    Type: Grant
    Filed: August 3, 2007
    Date of Patent: October 6, 2009
    Assignee: AU Optronics Corp.
    Inventors: Kung-hong Lee, Cheng-chiu Pai, Shi-hsiang Lu, Wein-town Sun
  • Publication number: 20080252362
    Abstract: A negative voltage converter includes six transistors. A first end and a control end of a first transistor are coupled to a signal input. A first end of a second transistor is coupled to the signal input, and a control end of which is coupled to a first clock and the first transistor. A first end of a third transistor is coupled to the signal input, a control end of the third transistor is coupled with a second clock and the second transistor. A first end of a fourth transistor is coupled to the second end of the third transistor, a control end of which is coupled with the first clock and the third transistor. A first end of a fifth transistor is coupled to the second end of the third transistor, and a control end of which is coupled with the second clock and the fourth transistor A first end of a sixth transistor is coupled to the second end of the third transistor, and a control end of which is coupled with the first clock and the fifth transistor.
    Type: Application
    Filed: August 3, 2007
    Publication date: October 16, 2008
    Applicant: AU Optronics Corp.
    Inventors: Kung-hong Lee, Cheng-chiu Pai, Shi-hsiang Lu, Wein-town Sun
  • Patent number: 6842374
    Abstract: An electrically erasable programmable logic device (EEPLD) contains a P-type substrate. A first N-type doped region is disposed in the P-type substrate. A first gate, which is used to store data, overlies the P-type substrate and is adjacent to the first N-type doped region. A second N-type doped region is laterally disposed in the P-type substrate. The second N-type doped region is also adjacent to the first gate. A second gate, which acts as a select gate or select gate of the EEPLD, overlies the P-type substrate and is adjacent to the second N-type doped region. A third N-type doped region is disposed in the P-type substrate. The third N-type doped region is adjacent to the second gate.
    Type: Grant
    Filed: January 6, 2003
    Date of Patent: January 11, 2005
    Assignee: eMemory Technology Inc.
    Inventors: Kung-Hong Lee, Ching-Hsiang Hsu, Ya-Chin King, Shih-Jye Shen, Ming-Chou Ho
  • Patent number: 6819594
    Abstract: An electrically erasable programmable logic device includes a P-type substrate, a first N-type doped region located inside the P-type substrate, and a first gate located on the P-type substrate. The first gate is adjacent to the first N-type doped region, is in a floating state, and is used for storing data. A second N-type doped region is located inside the P-type substrate adjacent to the first gate. A second gate is located on the P-type substrate and adjacent to the second N-type doped region and acts as a select gate. A third N-type doped region is located inside the P-type substrate adjacent to the second gate.
    Type: Grant
    Filed: January 6, 2003
    Date of Patent: November 16, 2004
    Assignee: eMemory Technology Inc.
    Inventors: Kung-Hong Lee, Ching-Hsiang Hsu, Ya-Chin King, Shih-Jye Shen, Ming-Chiu Ho
  • Publication number: 20040130950
    Abstract: An electrically erasable programmable logic device includes a P-type substrate, a first N-type doped region located inside the P-type substrate, and a first gate located on the P-type substrate. The first gate is adjacent to the first N-type doped region, is in a floating state, and is used for storing data. A second N-type doped region is located inside the P-type substrate adjacent to the first gate. A second gate is located on the P-type substrate and adjacent to the second N-type doped region and acts as a select gate. A third N-type doped region is located inside the P-type substrate adjacent to the second gate.
    Type: Application
    Filed: January 6, 2003
    Publication date: July 8, 2004
    Inventors: Kung-Hong Lee, Ching-Hsiang Hsu, Ya-Chin King, Shih-Jye Shen, Ming-Chou Ho
  • Publication number: 20040129985
    Abstract: An electrically erasable programmable logic device (EEPLD) contains a P-type substrate. A first N-type doped region is disposed in the P-type substrate. A first gate, which is used to store data, overlies the P-type substrate and is adjacent to the first N-type doped region. A second N-type doped region is laterally disposed in the P-type substrate. The second N-type doped region is also adjacent to the first gate. A second gate, which acts as a select gate or select gate of the EEPLD, overlies the P-type substrate and is adjacent to the second N-type doped region. A third N-type doped region is disposed in the P-type substrate. The third N-type doped region is adjacent to the second gate.
    Type: Application
    Filed: January 6, 2003
    Publication date: July 8, 2004
    Inventors: Kung-Hong Lee, Ching-Hsiang Hsu, Ya-Chin King, Shih-Jye Shen, Ming-Chou Ho
  • Patent number: 6580641
    Abstract: A method of forming and operating a trench split-gate non-volatile flash memory cell structure. The auxiliary gate of the structure is formed inside a trench on one side of the gate and the source terminal is underneath the auxiliary gate, thereby reducing overall area occupation of the auxiliary gate and the source terminal relative to the cell and increasing packing density. By enclosing the common source terminal inside a deep N-well layer, source resistance for reading data from the cell is reduced and the process of etching out a contact opening is simplified. The structure also ensures the injection of most hot electrons into the floating gate, thereby increasing execution speed.
    Type: Grant
    Filed: October 31, 2002
    Date of Patent: June 17, 2003
    Assignee: eMemory Technology Inc.
    Inventors: Meng-Yi Wu, Kung-Hong Lee, Fu-Yuan Chen, Hsin-Fen Chou, Ching-Song Yang, Ya-Chin Kin, Ching-Hsiang Hsu
  • Publication number: 20030086296
    Abstract: A method of forming and operating a trench split-gate non-volatile flash memory cell structure. The auxiliary gate of the structure is formed inside a trench on one side of the gate and the source terminal is underneath the auxiliary gate, thereby reducing overall area occupation of the auxiliary gate and the source terminal relative to the cell and increasing packing density. By enclosing the common source terminal inside a deep N-well layer, source resistance for reading data from the cell is reduced and the process of etching out a contact opening is simplified. The structure also ensures the injection of most hot electrons into the floating gate, thereby increasing execution speed.
    Type: Application
    Filed: October 31, 2002
    Publication date: May 8, 2003
    Inventors: Meng-Yi Wu, Kung-Hong Lee, Fu-Yuan Chen, Hsin-Fen Chou, Ching-Song Yang, Ya-Chin King, Ching-Hsiang Hsu
  • Publication number: 20030068845
    Abstract: A method for manufacturing a flash device having a trench source line comprises providing a semiconductor substrate. A pad oxide is formed on a substrate, then forming a nitride layer on the pad oxide. The nitride layer and the pad oxide layer are patterned then etching the substrate to form a trench in the substrate. An ion implantation is performed to dope ions into the substrate under the trench to form the trench source line. Next, refilling material is refilled into the trench, followed by performing chemical mechanical polishing to remove a portion of the refilling material to the substrate. A gate dielectric layer, a first doped conductive layer, an inter conductive dielectric layer, a second conductive layer are formed. The first conductive layer, the second conductive layer and the inter conductive dielectric layer are etched to form gate structure. Subsequently, source and drain regions are formed by ion implantation and halo-doped region is formed under the drain regions by ion implantation.
    Type: Application
    Filed: August 1, 2002
    Publication date: April 10, 2003
    Inventors: Fu-Yuan Chen, Ching-Hsiang Hsu, Ya-Chin King, Ching-Sung Yang, Hsiu-Fen Chou, Kung-Hong Lee, Meng-Yi Wu
  • Patent number: 6518126
    Abstract: A method of forming and operating a trench split-gate non-volatile flash memory cell structure. The auxiliary gate of the structure is formed inside a trench on one side of the gate and the source terminal is underneath the auxiliary gate, thereby reducing overall area occupation of the auxiliary gate and the source terminal relative to the cell and increasing packing density. By enclosing the common source terminal inside a deep N-well layer, source resistance for reading data from the cell is reduced and the process of etching out a contact opening is simplified. The structure also ensures the injection of most hot electrons into the floating gate, thereby increasing execution speed.
    Type: Grant
    Filed: April 23, 2002
    Date of Patent: February 11, 2003
    Assignee: eMemory Technology Inc.
    Inventors: Meng-Yi Wu, Kung-Hong Lee, Fu-Yuan Chen, Hsin-Fen Chou, Ching-Song Yang, Ya-Chin King, Ching-Hsiang Hsu
  • Patent number: 6490196
    Abstract: A flash memory cell with an embedded gate structure capable of storing two bits of information and the operation of such a flash memory cell are provided. A first ion-doped region, serving as a source terminal, is formed in a semiconductor substrate. An embedded gate structure and a second ion-doped region are alternately arranged on the first ion-doped region. The embedded gate structure is surrounded by the first oxide layer, the trapping layer, and the second oxide layer. An insulating layer is formed on the embedded gate structure. A diffusion drain is positioned atop the second ion-doped region and a conductive layer connects with the diffusion drains. The embedded gate structure is isolated from the diffusion drain with the insulating layer. Furthermore, the reading, programming, and erasing operation of the memory cell with two bits of information are provided.
    Type: Grant
    Filed: June 4, 2002
    Date of Patent: December 3, 2002
    Assignee: eMemory Technology Inc.
    Inventors: Ching-Hsiang Hsu, Kung-Hong Lee, Ching-Sung Yang
  • Publication number: 20020175394
    Abstract: A method of forming and operating a trench split-gate non-volatile flash memory cell structure. The auxiliary gate of the structure is formed inside a trench on one side of the gate and the source terminal is underneath the auxiliary gate, thereby reducing overall area occupation of the auxiliary gate and the source terminal relative to the cell and increasing packing density. By enclosing the common source terminal inside a deep N-well layer, source resistance for reading data from the cell is reduced and the process of etching out a contact opening is simplified. The structure also ensures the injection of most hot electrons into the floating gate, thereby increasing execution speed.
    Type: Application
    Filed: April 23, 2002
    Publication date: November 28, 2002
    Inventors: Meng-Yi Wu, Kung-Hong Lee, Fu-Yuan Chen, Hsin-Fen Chou, Ching-Song Yang, Ya-Chin King, Ching-Hsiang Hsu
  • Patent number: 6448607
    Abstract: A flash memory cell with an embedded gate structure capable of storing two bits of information and the operation of such a flash memory cell are provided. A first ion-doped region, serving as a source terminal, is formed in a semiconductor substrate. An embedded gate structure and a second ion-doped region are alternately arranged on the first ion-doped region. The embedded gate structure is surrounded by the first oxide layer, the trapping layer, and the second oxide layer. An insulating layer is formed on the embedded gate structure. A diffusion drain is positioned atop the second ion-doped region and a conductive layer connects with the diffusion drains. The embedded gate structure is isolated from the diffusion drain with the insulating layer. Furthermore, the reading, programming, and erasing operation of the memory cell with two bits of information are provided.
    Type: Grant
    Filed: December 3, 2001
    Date of Patent: September 10, 2002
    Assignee: eMemory Technology Inc.
    Inventors: Ching-Hsiang Hsu, Kung-Hong Lee, Ching-Sung Yang
  • Publication number: 20020071315
    Abstract: A flash memory cell with an embedded gate structure capable of storing two bits of information and the operation of such a flash memory cell are provided. A first ion-doped region, serving as a source terminal, is formed in a semiconductor substrate. An embedded gate structure and a second ion-doped region are alternately arranged on the first ion-doped region. The embedded gate structure is surrounded by the first oxide layer, the trapping layer, and the second oxide layer. An insulating layer is formed on the embedded gate structure. A diffusion drain is positioned atop the second ion-doped region and a conductive layer connects with the diffusion drains. The embedded gate structure is isolated from the diffusion drain with the insulating layer. Furthermore, the reading, programming, and erasing operation of the memory cell with two bits of information are provided.
    Type: Application
    Filed: December 3, 2001
    Publication date: June 13, 2002
    Inventors: Ching-Hsiang Hsu, Kung-Hong Lee, Ching-Sung Yang